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    • 33. 发明授权
    • Reset circuit
    • 复位电路
    • US07545186B2
    • 2009-06-09
    • US10998060
    • 2004-11-29
    • Hideaki SuzukiHirokazu Yamazaki
    • Hideaki SuzukiHirokazu Yamazaki
    • H02H3/24
    • H03K17/223H03K3/356008
    • A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.
    • 复位电路包括电源检测电路,掉电检测电路和输出电路。 当电源电压的第一电压高于第一阈值时,电源检测电路输出第一信号,并且在上电和掉电期间当第一电压低于第一阈值时输出第二信号。 当在掉电期间输出第二信号之后,当根据电源电压的第二电压变得低于第二阈值时,掉电检测电路输出第三信号。 输出电路在上电时输出第一个信号时,输出从低电平变为高电平的上电复位信号,并在断电时输出第三个信号输出时从低电平变为高电平的掉电复位信号 。
    • 34. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US07280384B2
    • 2007-10-09
    • US11072241
    • 2005-03-07
    • Hideaki Suzuki
    • Hideaki Suzuki
    • G11C11/22
    • G11C11/22
    • In a semiconductor memory device including memory cells respective having a ferroelectric capacitor, and are provided at intersection portions of sets of a plurality of word lines and plate lines which is adjacent thereto, with bit lines, clamp circuits are respectively connected between the bit lines and nodes being supplied with reference potentials. Herewith, electric charges supplied from the ferroelectric capacitors to the bit lines are extracted by the clamp circuits, and capacities of the bit lines are increased artificially. Consequently, during a data read operation, an amount of electric potential change of the bit lines according to stored data in the ferroelectric capacitors is improved, and it becomes possible to obtain a large potential difference between the bit lines.
    • 在包括各自具有铁电电容器的存储单元的半导体存储器件中,并且在与位线相邻的多个字线和板线的组的交叉部分处设置有位线,钳位电路分别连接在位线和 节点被提供参考电位。 由此,由钳位电路提取从铁电电容器向位线提供的电荷,并且人为地增加位线的容量。 因此,在数据读取操作期间,提高了根据铁电电容器中存储的数据的位线的电位变化量,并且可以获得位线之间的大的电位差。
    • 38. 发明申请
    • Output control device of generation device
    • 发电装置的输出控制装置
    • US20060097703A1
    • 2006-05-11
    • US11263809
    • 2005-11-01
    • Hideaki SuzukiMasakatsu TakahashiShuichi MuramatsuTomohiro Nakagawa
    • Hideaki SuzukiMasakatsu TakahashiShuichi MuramatsuTomohiro Nakagawa
    • H02H7/06H02P9/00H02P11/00
    • H02P9/48
    • An output control device of a generation device including: a rectifier circuit that rectifies an output of an AC generator and applies the output across a battery; an inverter circuit provided between the battery and the generator; inverter control means for controlling the inverter circuit to convert a voltage across the battery into an AC control voltage and apply the voltage to an armature winding of the generator; and phase detection means for detecting a phase of a phase current flowing through the armature winding of the generator as a maximum output current phase, wherein the inverter control means is comprised to control a phase of the AC control voltage so as not to be delayed with respect to the maximum output current phase, and thus prevent a reduction in the output of the generator caused by an excessive delay of the phase of the AC control voltage.
    • 1.一种发电装置的输出控制装置,包括:整流电路,对交流发电机的输出进行整流,并将输出施加于电池; 设置在电池和发电机之间的逆变器电路; 逆变器控制装置,用于控制逆变器电路将电池两端的电压转换成AC控制电压,并将电压施加到发电机的电枢绕组; 以及相位检测装置,用于检测流过发电机的电枢绕组的相电流的相位作为最大输出电流相位,其中逆变器控制装置包括用于控制AC控制电压的相位,以便不会随着 相对于最大输出电流相位,从而防止由交流控制电压的相位的过度延迟引起的发电机的输出的减小。
    • 39. 发明申请
    • Reset circuit
    • 复位电路
    • US20050275437A1
    • 2005-12-15
    • US10998060
    • 2004-11-29
    • Hideaki SuzukiHirokazu Yamazaki
    • Hideaki SuzukiHirokazu Yamazaki
    • H03K3/356H03K17/22H03L7/00
    • H03K17/223H03K3/356008
    • A reset circuit includes a power supply detection circuit, a power-down detection circuit, and an output circuit. The power supply detection circuit outputs a first signal when a first voltage according to a power supply voltage is higher than a first threshold and outputting a second signal when the first voltage is lower than the first threshold during power-on and power-down. The power-down detection circuit outputs a third signal when a second voltage according to the power supply voltage becomes lower than a second threshold after the second signal is outputted during power-down. The output circuit outputs a power-on reset signal which changes from low to high when the first signal is outputted during power-on and outputs a power-down reset signal which changes from low to high when the third signal is outputted during power-down.
    • 复位电路包括电源检测电路,掉电检测电路和输出电路。 当电源电压的第一电压高于第一阈值时,电源检测电路输出第一信号,并且在上电和掉电期间当第一电压低于第一阈值时输出第二信号。 当在掉电期间输出第二信号之后,当根据电源电压的第二电压变得低于第二阈值时,掉电检测电路输出第三信号。 输出电路在上电时输出第一个信号时,输出从低电平变为高电平的上电复位信号,并在断电时输出第三个信号输出时从低电平变为高电平的掉电复位信号 。
    • 40. 发明授权
    • Semiconductor memory device
    • 半导体存储器件
    • US06950326B2
    • 2005-09-27
    • US10644040
    • 2003-08-20
    • Hideaki Suzuki
    • Hideaki Suzuki
    • G11C11/22
    • G11C11/22
    • After a read operation is conducted to a memory area designated by an address in response to a combination of a data destructive signal and a chip select signal, a bit line is pre-charged with a ground potential and an electric potential of a plate line is lowered, thereby stopping the data from being written back to an area in which the data is destroyed by the read operation. The electric potential of the word line may be kept at VDD level without boosting it to a potential for writing back the data. The bit line may be clamped to the ground potential, thereby stopping the read data from being output to an outside of a memory device to stop an operation of a sense amplifier.
    • 在响应于数据破坏性信号和片选信号的组合对地址指定的存储区域进行读取操作之后,位线被预充电地电位,并且板线的电位为 降低,从而停止将数据写回到读取操作中数据被破坏的区域。 字线的电位可以保持在VDD电平,而不会将其提高到写回数据的可能性。 位线可能被钳位到地电位,从而停止读取数据输出到存储器件的外部,以停止读出放大器的操作。