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    • 34. 发明授权
    • Mechanical speed measuring device for a beach buggy
    • 沙滩车的机械速度测量装置
    • US06553854B2
    • 2003-04-29
    • US09948540
    • 2001-09-10
    • Michael YuJeff HuangJudge FuTony Chen
    • Michael YuJeff HuangJudge FuTony Chen
    • F16H3700
    • G01P1/026G01P3/48
    • A speed measuring device for a beach buggy includes a chain wheel rotated by the engine of a buggy, a connecting tube firmly connected to the chain wheel, a bearing fitted in the connecting tube, a gear set, and a fixing unit combined together. The fixing plate, the gear set, the connecting tube and the bearing are assembled together with an elongate rod with thread formed in the lower end portion and then fixed with the chain wheel. Then a hole base is formed on a rear small diameter portion of the gear set for a cable to extend in to transmit speed of the rotating chain wheel to a speedometer for a user to know the speed of the beach buggy.
    • 用于沙滩车的速度测量装置包括由马车的发动机旋转的链轮,牢固地连接到链轮的连接管,装配在连接管中的轴承,齿轮组和固定单元组合在一起。 固定板,齿轮组,连接管和轴承与细长杆组装在一起,螺杆形成在下端部分,然后用链轮固定。 然后,在用于电缆的齿轮组的后部小直径部分上形成孔底座,以延伸以将旋转链轮的速度传递到速度计,以使用户知道沙滩车的速度。
    • 36. 发明授权
    • Pulse wordline control circuit and method for a computer memory device
    • 用于计算机存储设备的脉冲字线控制电路和方法
    • US5959934A
    • 1999-09-28
    • US137176
    • 1998-08-20
    • Tony ChenJowsoon Hsu
    • Tony ChenJowsoon Hsu
    • G11C8/08G11C8/18G11C11/413G11C8/00G11C16/04
    • G11C8/18G11C11/413G11C8/08
    • A PWL control circuit and method is provided for use on a memory device to control the high/low logic state of the wordlines connected to the memory cell array of the memory device during access operation. The memory device can be a DRAM (dynamic random-access memory) device or an SRAM (static random-access memory device). The PWL control circuit and method utilizes a feedback signal from the sense amplifier to control the high/low logic state of the wordlines of the memory device. This feature can help eliminate the problem of an early deactivation of the currently activated wordlines during access operation that would otherwise occur when using the RC delay circuit in the prior art. Therefore, even if process parameters of the memory device are changed, the reliable sensing of the data from the memory cells is not affected.
    • 提供一种用于存储器件的PWL控制电路和方法,以在访问操作期间控制连接到存储器件的存储单元阵列的字线的高/低逻辑状态。 存储器件可以是DRAM(动态随机存取存储器)器件或SRAM(静态随机存取存储器件)。 PWL控制电路和方法利用来自读出放大器的反馈信号来控制存储器件的字线的高/低逻辑状态。 该功能可以帮助消除在使用现有技术中的RC延迟电路时可能发生的访问操作期间对当前激活的字线的早期停用的问题。 因此,即使改变存储器件的处理参数,也不会影响来自存储器单元的数据的可靠感测。