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31. 发明申请

US20120290826A1 BOOTING IN SYSTEMS HAVING DEVICES COUPLED IN A CHAINED CONFIGURATION 有权
标题翻译：在具有连接配置中的设备的系统中进行操作
公开(公告)号：US20120290826A1
公开(公告)日：2012-11-15
申请号：US13559162
申请日：2012-07-26
申请人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： G06F9/00
CPC分类号： G06F9/4411 , G06F9/4401
摘要： The present disclosure includes methods, devices, and systems for booting in systems having devices coupled in a chained configuration. One or more embodiments include a host and a number of devices coupled to the host in a chained configuration, wherein at least one of the number of devices is a bootable device and the at least one bootable device is not directly coupled to the host.
摘要翻译：本公开包括用于在具有以链接配置耦合的设备的系统中引导的方法，设备和系统。一个或多个实施例包括以链接配置耦合到主机的主机和多个设备，其中，多个设备中的至少一个是可引导设备，并且所述至少一个可启动设备不直接耦合到主机。

32. 发明申请

US20120284466A1 METHODS FOR CONTROLLING HOST MEMORY ACCESS WITH MEMORY DEVICES AND SYSTEMS 有权
标题翻译：用于利用存储器件和系统来控制存储器存取的方法
公开(公告)号：US20120284466A1
公开(公告)日：2012-11-08
申请号：US13550671
申请日：2012-07-17
申请人： Neal A. Galbo , Peter Feeley , William H. Radke , Victor Y. Tsai , Robert N. Leibowitz
发明人： Neal A. Galbo , Peter Feeley , William H. Radke , Victor Y. Tsai , Robert N. Leibowitz
IPC分类号： G06F12/00
CPC分类号： G06F3/0604 , G06F3/0659 , G06F3/0683 , G06F13/1642
摘要： The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.
摘要翻译：本公开包括用于使用存储设备，系统，主机控制器和存储设备来控制主机存储器访问的方法。用于使用存储器设备控制主机存储器访问的一个实施例包括从主机接收至少一个命令并且用该存储器设备控制至少一个命令的执行。

33. 发明授权

US08295109B2 Replacing defective columns of memory cells in response to external addresses 有权
标题翻译：根据外部地址更换存储单元的有缺陷的列
公开(公告)号：US08295109B2
公开(公告)日：2012-10-23
申请号：US13017168
申请日：2011-01-31
申请人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
发明人： Vishal Sarin , William H. Radke , Dzung H. Nguyen
IPC分类号： G11C29/00
CPC分类号： G11C29/848
摘要： Controllers and memory devices are provided. In an embodiment, a controller is configured to address a non-defective column of memory cells of a memory device in place of a defective column of memory cells of the memory device in response to receiving an address of the defective column of memory cells from the memory device. In another embodiment, a memory device has columns of memory cells and is configured to receive an external address that addresses a non-defective column of memory cells of a sequence of columns of memory cells of the memory device in place of a defective column of memory cells of the sequence of columns of memory cells such that the non-defective column replaces the defective column. The non-defective column is a proximate non-defective column following the defective column in the sequence of columns that is available to replace the defective column.
摘要翻译：提供控制器和存储器件。在一个实施例中，控制器被配置为响应于接收来自存储器单元的存储器单元的缺陷列的地址，来代替存储器件的存储器单元的无缺陷列来代替存储器件的存储器单元的缺陷列存储设备。在另一个实施例中，存储器设备具有存储单元的列，并且被配置为接收寻址存储器件的存储器单元列序列的无缺陷列的存储器单元的外部地址，而不是缺陷存储器列存储单元列的序列的单元，使得无缺陷列替代缺陷列。无缺陷列是可用于替换缺陷列的列序列中的缺陷列之后的邻近无缺陷列。

34. 发明授权

US08225052B2 Methods for controlling host memory access with memory devices and systems 有权
标题翻译：使用内存设备和系统控制主机内存访问的方法
公开(公告)号：US08225052B2
公开(公告)日：2012-07-17
申请号：US12477204
申请日：2009-06-03
申请人： Neal A. Galbo , Peter Feeley , William H. Radke , Victor Y. Tsai , Robert N. Leibowitz
发明人： Neal A. Galbo , Peter Feeley , William H. Radke , Victor Y. Tsai , Robert N. Leibowitz
IPC分类号： G06F12/00
CPC分类号： G06F3/0604 , G06F3/0659 , G06F3/0683 , G06F13/1642
摘要： The present disclosure includes methods for controlling host memory access with a memory device, systems, host controllers and memory devices. One embodiment for controlling host memory access with a memory device includes receiving at least one command from a host and controlling execution of the at least one command with the memory device.
摘要翻译：本公开包括用于使用存储设备，系统，主机控制器和存储设备来控制主机存储器访问的方法。用于使用存储器设备控制主机存储器访问的一个实施例包括从主机接收至少一个命令并且用该存储器设备控制至少一个命令的执行。

35. 发明授权

US08189420B2 Advanced detection of memory device removal, and methods, devices and connectors 有权
标题翻译：高级检测存储器件拆卸，以及方法，设备和连接器
公开(公告)号：US08189420B2
公开(公告)日：2012-05-29
申请号：US12478422
申请日：2009-06-04
申请人： James Cooke , Peter Feeley , Victor Tsai , William H. Radke , Neal Galbo , Chad Cobbley
发明人： James Cooke , Peter Feeley , Victor Tsai , William H. Radke , Neal Galbo , Chad Cobbley
IPC分类号： G11C5/14
CPC分类号： G06F13/4068
摘要： Memory devices, connectors and methods for terminating an operation are provided, including a memory device configured to terminate an internal operation such as a programming or erase operation responsive to receiving a signal during removal of the memory device from a connector, such as a socket. The memory device may be specially configured to generate the removal signal, such as by including a dedicated removal terminal. The memory card may respond to the signal by terminating a programming or erase operation before power is lost. The removal terminal may have a dimension that is different from a dimension of a power terminal through which the memory device receives power. Alternatively, the connector may be specially configured to generate a signal that causes a host to terminate programming or erase operations in the memory device prior to memory card removal, such as by including a switch that is actuated when the memory device moves to a pre-power loss position.
摘要翻译：提供了用于终止操作的存储器件，连接器和方法，包括响应于在从诸如插座的连接器移除存储器设备期间接收信号而终止诸如编程或擦除操作之类的内部操作的存储器件。存储器件可以被特别地配置为产生去除信号，例如通过包括专用的移除终端。存储卡可以通过在断电之前终止编程或擦除操作来响应信号。移除终端可以具有不同于存储设备通过其接收电力的功率端子的尺寸的尺寸。或者，连接器可以被特别地配置成产生一个信号，使得主机在存储卡移除之前终止在存储器设备中的编程或擦除操作，例如通过包括当存储器件移动到预定位置时被致动的开关，断电位置

36. 发明申请

US20120030545A1 ERROR RECOVERY STORAGE ALONG A NAND-FLASH STRING 有权
标题翻译： NAND闪存盘中的错误恢复存储
公开(公告)号：US20120030545A1
公开(公告)日：2012-02-02
申请号：US13267262
申请日：2011-10-06
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： H03M13/05 , G06F11/10
CPC分类号： G06F11/1008 , G06F11/1072 , H03M13/256 , H03M13/2909
摘要： Apparatus and methods store error recovery data in different dimensions of a memory array. For example, in one dimension, block error correction codes (ECC) are used, and in another dimension, supplemental error correction codes, such as convolutional codes, are used. By using separate dimensions, the likelihood that a defect affects both error recovery techniques is lessened, thereby increasing the probability that error recovery can be performed successfully. In one example, block error correction codes are used for data stored along rows, and this data is stored in one level of multiple-level cells of the array. Supplemental error correction codes are used for data stored along columns, such as along the cells of a string, and the supplemental error correction codes are stored in a different level than the error correction codes.
摘要翻译：设备和方法存储存储器阵列的不同维度的错误恢复数据。例如，在一个维度中，使用块纠错码（ECC），并且在另一维度中，使用补码纠错码，例如卷积码。通过使用单独的维度，缺陷影响两种错误恢复技术的可能性减弱，从而增加了可以成功执行错误恢复的概率。在一个示例中，块错误校正码用于沿着行存储的数据，并且该数据被存储在阵列的多级单元中。补充纠错码用于沿列存储的数据，例如沿着字符串的单元格，并且补充纠错码存储在与纠错码不同的电平上。

37. 发明授权

US07930612B2 Error detection and correction scheme for a memory device 有权
标题翻译：存储器件的错误检测和校正方案
公开(公告)号：US07930612B2
公开(公告)日：2011-04-19
申请号：US11706506
申请日：2007-02-15
申请人： William H. Radke , Shuba Swaminathan , Brady L. Keays
发明人： William H. Radke , Shuba Swaminathan , Brady L. Keays
IPC分类号： G11C29/00 , H03M13/29
CPC分类号： H03M13/096 , G06F11/1008
摘要： Data is read from a memory array. Before being stored in a data buffer, a Hamming code detection operation and a Reed-Solomon code detection operation are operated in parallel to determine if the data word has any errors. The results of the parallel detection operations are communicated to a controller circuit. If an error is present that can be corrected by the Hamming code correction operation, this is performed and the Reed-Solomon code detection operation is performed on the corrected word. If the error is uncorrectable by the Hamming code, the Reed-Solomon code correction operation is performed on the word.
摘要翻译：从存储器阵列中读取数据。在存储在数据缓冲器中之前，并行地操作汉明码检测操作和里德 - 所罗门码检测操作，以确定数据字是否具有任何错误。并行检测操作的结果被传送到控制器电路。如果存在可以通过汉明码校正操作来校正的错误，则执行该校正字，并且对校正字执行里德 - 所罗门码检测操作。如果汉明码不能校正错误，则对该字执行里德 - 所罗门码修正操作。

38. 发明申请

US20110063907A1 FRACTIONAL BITS IN MEMORY CELLS 有权
标题翻译：记忆细胞中的分位
公开(公告)号：US20110063907A1
公开(公告)日：2011-03-17
申请号：US12949347
申请日：2010-11-18
申请人： William H. Radke
发明人： William H. Radke
IPC分类号： G11C16/04 , G11C16/26 , G11C16/10
CPC分类号： G11C11/5628 , G06F11/1008 , G11C11/5621 , G11C11/5642 , G11C16/04 , G11C16/0483 , G11C16/10 , G11C29/00 , G11C2211/5641
摘要： Methods, devices, modules, and systems for programming memory cells can include storing charges corresponding to a data state that represents an integer number of bits in a set of memory cells. Programming memory cells can include storing a charge in a cell of the set, where the charge corresponds to a programmed state, where the programmed state represents a fractional number of bits, and where the programmed state denotes a digit of the data state as expressed by a number in base N, where N is equal to 2B, rounded up to an integer, and where B is equal to the fractional number of bits represented by the programmed state.
摘要翻译：用于编程存储器单元的方法，设备，模块和系统可以包括存储与在一组存储器单元中表示整数位的数据状态相对应的电荷。编程存储器单元可以包括将电荷存储在组的单元中，其中电荷对应于编程状态，其中编程状态表示分数位数，并且其中编程状态表示数据状态的数字，如基数N中的数，其中N等于2B，向上舍入为整数，并且其中B等于由编程状态表示的分数的位数。

39. 发明申请

US20110055436A1 DEVICE TO DEVICE FLOW CONTROL 有权
标题翻译：设备流量控制的设备
公开(公告)号：US20110055436A1
公开(公告)日：2011-03-03
申请号：US12550770
申请日：2009-08-31
申请人： Victor Y. Tsai , William H. Radke , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： Victor Y. Tsai , William H. Radke , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： G06F3/00
CPC分类号： H04L47/215 , H04L47/10 , H04L47/17
摘要： The present disclosure includes methods, devices, and systems for device to device flow control. In one or more embodiments, a system configured for device to device flow control includes a host and a chain of devices, including one or more memory device, coupled to each other and configured to communicate with the host device through a same host port. In one or more embodiments, at least one device in the chain is configured to regulate the flow of data by sending a token in downstream data packets, the token allowing devices downstream from the respective at least one device to send an upstream data packet to the respective at least one device.
摘要翻译：本公开包括用于设备到设备流控制的方法，设备和系统。在一个或多个实施例中，被配置用于设备到设备流控制的系统包括主机和一连串设备，包括一个或多个存储器设备，它们彼此耦合并被配置为通过相同的主机端口与主机设备进行通信。在一个或多个实施例中，链中的至少一个设备被配置为通过在下游数据分组中发送令牌来调节数据流，该令牌允许来自相应的至少一个设备的下游的设备将上游数据分组发送到各自至少一个设备。

40. 发明申请

US20110032823A1 PACKET DECONSTRUCTION/RECONSTRUCTION AND LINK-CONTROL 有权
标题翻译：分组分解/重构和链接控制
公开(公告)号：US20110032823A1
公开(公告)日：2011-02-10
申请号：US12538607
申请日：2009-08-10
申请人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
发明人： William H. Radke , Victor Y. Tsai , Peter Feeley , Neal A. Galbo , Robert N. Leibowitz
IPC分类号： H04L12/56
CPC分类号： H04L47/34 , H04L1/1867 , H04L47/27 , H04L69/324
摘要： The present disclosure includes methods, devices, and systems for packet processing. One method embodiment for packet flow control includes deconstructing a transport layer packet into a number of link-control layer packets, wherein each of the link-control layer packets has an associated sequence number, communicating the number of link-control layer packets via a common physical connection for a plurality of peripheral devices, and limiting a number of outstanding link-control layer packets during the communication.
摘要翻译：本公开包括用于分组处理的方法，设备和系统。用于分组流控制的一个方法实施例包括将传输层分组解构成多个链路控制层分组，其中链路控制层分组中的每一个具有相关联的序列号，经由共同的通信来传送链路控制层分组的数量用于多个外围设备的物理连接，并且在通信期间限制多个未完成的链路控制层分组。

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