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31. 发明申请

US20110254067A1 DRAM Layout with Vertical FETS and Method of Formation 有权
标题翻译：具有垂直FET的DRAM布局和形成方法
公开(公告)号：US20110254067A1
公开(公告)日：2011-10-20
申请号：US13170050
申请日：2011-06-27
申请人： Todd R. Abbott , Homer M. Manning
发明人： Todd R. Abbott , Homer M. Manning
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10808 , H01L27/10876 , Y10S257/908
摘要： DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有约4F2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。至少一个掩埋位线与垂直晶体管的至少一个垂直栅电极正交。

32. 发明申请

US20110244404A1 Photoresist Processing Methods 有权
公开(公告)号：US20110244404A1
公开(公告)日：2011-10-06
申请号：US13163515
申请日：2011-06-17
申请人： Kevin J. Torek , Todd R. Abbott , Sandra Tagg , Amy Weatherly
发明人： Kevin J. Torek , Todd R. Abbott , Sandra Tagg , Amy Weatherly
IPC分类号： G03F7/20
CPC分类号： H01L21/32139 , G03F7/16 , G03F7/322 , H01L21/0271
摘要： A photoresist processing method includes treating a substrate with a sulfur-containing substance. A positive-tone photoresist is applied on and in contact with the treated substrate. The method includes selectively exposing a portion of the photoresist to actinic energy and developing the photoresist to remove the exposed portion and to form a photoresist pattern on the substrate. The treating with a sulfur-containing substance reduces an amount of residual photoresist intended for removal compared to an amount of residual photoresist that remains without the treating.

33. 发明授权

US07989866B2 DRAM layout with vertical FETS and method of formation 有权
标题翻译： DRAM布局采用垂直FETS和形成方法
公开(公告)号：US07989866B2
公开(公告)日：2011-08-02
申请号：US12568240
申请日：2009-09-28
申请人： Todd R. Abbott , Homer M. Manning
发明人： Todd R. Abbott , Homer M. Manning
IPC分类号： H01L27/108
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10808 , H01L27/10876 , Y10S257/908
摘要： DRAM cell arrays having a cell area of about 4 F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有约4F2单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。至少一个掩埋位线与垂直晶体管的至少一个垂直栅电极正交。

34. 发明授权

US07736969B2 DRAM layout with vertical FETS and method of formation 有权
标题翻译： DRAM布局采用垂直FETS和形成方法
公开(公告)号：US07736969B2
公开(公告)日：2010-06-15
申请号：US11257157
申请日：2005-10-25
申请人： Todd R. Abbott , Homer M. Manning
发明人： Todd R. Abbott , Homer M. Manning
IPC分类号： H01L21/8242
CPC分类号： H01L27/10885 , H01L21/28132 , H01L27/10808 , H01L27/10876 , Y10S257/908
摘要： DRAM cell arrays having a cell area of about 4F2 comprise an array of vertical transistors with buried bit lines and vertical double gate electrodes. The buried bit lines comprise a silicide material and are provided below a surface of the substrate. The word lines are optionally formed of a silicide material and form the gate electrode of the vertical transistors. The vertical transistor may comprise sequentially formed doped polysilicon layers or doped epitaxial layers. At least one of the buried bit lines is orthogonal to at least one of the vertical gate electrodes of the vertical transistors.
摘要翻译：具有约4F2的单元面积的DRAM单元阵列包括具有掩埋位线和垂直双栅电极的垂直晶体管阵列。掩埋位线包括硅化物材料并且被设置在衬底的表面下方。字线可选地由硅化物材料形成并形成垂直晶体管的栅电极。垂直晶体管可以包括顺序形成的掺杂多晶硅层或掺杂的外延层。至少一个掩埋位线与垂直晶体管的至少一个垂直栅电极正交。

35. 发明授权

US07348236B2 Formation of memory cells and select gates of NAND memory arrays 有权
标题翻译：存储单元的形成和NAND存储器阵列的选择门
公开(公告)号：US07348236B2
公开(公告)日：2008-03-25
申请号：US10878799
申请日：2004-06-28
申请人： Todd R. Abbott , Michael Violette
发明人： Todd R. Abbott , Michael Violette
IPC分类号： H01L21/336
CPC分类号： H01L27/11521 , H01L27/115
摘要： Apparatus and methods are provided. Floating-gate memory cells and select gates of NAND memory arrays are formed concurrently by anisotropically removing portions of a second conductive layer disposed on a first conductive layer such that remaining portions of the second conductive layer self align with and are disposed on sidewalls of the first conductive layer. The first conductive layer is disposed on a first dielectric layer that is disposed on a substrate. A second dielectric layer is formed overlying the first conductive layer and the remaining portions of the second conductive layer. A third conductive layer is formed on the second dielectric layer. A fourth conductive layer is formed on the third conductive layer. For the select gate, the fourth conductive layer also passes through the third conductive layer and the second dielectric layer to electrically connect the conductive layers.
摘要翻译：提供了装置和方法。浮动栅存储器单元和NAND存储器阵列的选择栅极通过各向异性地去除设置在第一导电层上的第二导电层的部分同时形成，使得第二导电层的剩余部分与第一导电层的侧壁对准并设置在第一导电层的侧壁上导电层。第一导电层设置在设置在基板上的第一介电层上。第二介电层形成在第一导电层和第二导电层的其余部分之上。在第二电介质层上形成第三导电层。在第三导电层上形成第四导电层。对于选择栅极，第四导电层还穿过第三导电层和第二介电层以电连接导电层。

36. 发明授权

US07153731B2 Method of forming a field effect transistor with halo implant regions 有权
标题翻译：用卤素注入区域形成场效应晶体管的方法
公开(公告)号：US07153731B2
公开(公告)日：2006-12-26
申请号：US10236662
申请日：2002-09-05
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/336 , H01L21/331 , H01L21/76 , H01L21/3205 , H01L21/44
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：形成场效应晶体管的方法包括在半导体衬底的本体半导体材料内形成沟道区。源极/漏极区域形成在沟道区域的相对侧上。绝缘电介质区域在本体半导体材料内形成在源极/漏极区域中的至少一个附近。形成场效应晶体管的方法包括提供绝缘体上半导体衬底，所述衬底包括在绝缘材料层上形成的半导体材料层。半导体材料层的一部分和直接在该部分正下方的所有绝缘材料层被除去，从而在半导体材料层和绝缘材料层中产生空隙。半导体通道材料形成在空隙内。相邻的源极/漏极区域横向靠近通道材料提供。在通道材料上形成一个栅极。集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

37. 发明授权

US07112482B2 Method of forming a field effect transistor 有权
公开(公告)号：US07112482B2
公开(公告)日：2006-09-26
申请号：US10901538
申请日：2004-07-28
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L21/8238
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： A method of forming a field effect transistor includes forming a channel region within bulk semiconductive material of a semiconductor substrate. Source/drain regions are formed on opposing sides of the channel region. An insulative dielectric region is formed within the bulk semiconductive material proximately beneath at least one of the source/drain regions. A method of forming a field effect transistor includes providing a semiconductor-on-insulator substrate, said substrate comprising a layer of semiconductive material formed over a layer of insulative material. All of a portion of the semiconductive material layer and all of the insulative material layer directly beneath the portion are removed thereby creating a void in the semiconductive material layer and the insulative material layer. Semiconductive channel material is formed within the void. Opposing source/drain regions are provided laterally proximate the channel material. A gate is formed over the channel material. Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.

38. 发明授权

US06987291B2 Integrated transistor circuitry 失效
标题翻译：集成晶体管电路
公开(公告)号：US06987291B2
公开(公告)日：2006-01-17
申请号：US10236282
申请日：2002-09-05
申请人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
发明人： Todd R. Abbott , Zhongze Wang , Jigish D. Trivedi , Chih-Chen Cho
IPC分类号： H01L31/0328
CPC分类号： H01L29/66651 , H01L21/26533 , H01L29/0653 , H01L29/41766 , H01L29/66636
摘要： Integrated circuitry includes a bulk semiconductor substrate. A field effect transistor thereon includes a gate, a channel region in the bulk semiconductor substrate, and source/drain regions within the substrate on opposing sides of the channel region. A field isolation region is formed in the bulk semiconductor substrate and laterally adjoins with one of the source/drain regions. The field isolation region includes a portion which extends beneath at least some of the one source/drain region. Other aspects are contemplated.
摘要翻译：集成电路包括体半导体衬底。其中的场效应晶体管包括栅极，体半导体衬底中的沟道区，以及在沟道区的相对侧上的衬底内的源极/漏极区。在体半导体衬底中形成场隔离区域，并且与源极/漏极区域之一横向邻接。场隔离区域包括在一个源极/漏极区域中的至少一些的下方延伸的部分。考虑其他方面。

39. 发明授权

US06333254B1 Methods of forming a local interconnect method of fabricating integrated circuitry comprising an SRAM cell having a local interconnect and having circuitry peripheral to the SRAM cell and method of forming contact plugs 失效
标题翻译：形成集成电路的局部互连方法的方法，该集成电路包括具有局部互连并且具有SRAM单元的外围电路的SRAM单元和形成接触插塞的方法
公开(公告)号：US06333254B1
公开(公告)日：2001-12-25
申请号：US09737919
申请日：2000-12-14
申请人： Todd R. Abbott , Michael P. Violette , Charles H. Dennison
发明人： Todd R. Abbott , Michael P. Violette , Charles H. Dennison
IPC分类号： H01L214763
CPC分类号： H01L27/11 , H01L21/76877 , H01L21/76895 , H01L27/1104
摘要： In one implementation, a substrate is provided which has at least two nodes to be electrically connected. A first conductivity type semiconductive material is formed over and in electrical connection with one of the nodes. A conductive diffusion barrier material is formed over and in electrical connection with the first conductivity type semiconductive material. A second conductivity type semiconductive material is formed over and in electrical connection with the first conductivity type semiconductive material through the conductive diffusion barrier material, and over and in electrical connection with another of the nodes. The first conductivity type semiconductive material, the conductive diffusion barrier material and the second conductivity type semiconductive material are formed into a local interconnect electrically connecting the one node and the another node. Local interconnects fabricated by this and other methods are also contemplated. The invention includes in one implementation a method of forming contact plugs.
摘要翻译：在一个实施方案中，提供了具有至少两个要电连接的节点的基板。第一导电类型的半导体材料形成在节点之一上并与其中的一个节点电连接。导电扩散阻挡材料形成在第一导电类型半导体材料之上并与第一导电类型的半导体材料电连接。第二导电类型半导体材料通过导电扩散阻挡材料形成在第一导电类型半导体材料之上并与电连接，并且与另一节点电连接。第一导电型半导体材料，导电扩散阻挡材料和第二导电类型半导体材料形成为电连接一个节点和另一个节点的局部互连。也可以设想通过该方法和其它方法制造的局部互连。本发明在一个实施方案中包括形成接触塞的方法。

40. 发明授权

US5869360A Method for forming a thin film transistor 失效
公开(公告)号：US5869360A
公开(公告)日：1999-02-09
申请号：US723945
申请日：1996-09-26
申请人： Shubneesh Batra , Monte Manning , Todd R. Abbott
发明人： Shubneesh Batra , Monte Manning , Todd R. Abbott
IPC分类号： H01L21/336 , H01L29/786 , H01L21/84
CPC分类号： H01L29/66757 , H01L29/78624 , Y10S438/97
摘要： A method for forming a field effect transistor which includes providing a substrate having thin film source and drain regions formed thereon; forming a thin film channel region intermediate the thin film source and drain regions, the thin film channel region comprising a first layer of semiconductor material, an etch stop layer formed over the first layer semiconductor material, and a second layer of material formed over the etch stop layer; forming a masking layer over the source and drain regions while leaving the thin film channel region effectively exposed; and removing a portion of the second layer of material selectively relative to the etch stop layer in the exposed thin film channel region.

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