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31. 发明授权

US07469372B2 Scan sequenced power-on initialization 有权
标题翻译：扫描顺序上电初始化
公开(公告)号：US07469372B2
公开(公告)日：2008-12-23
申请号：US11381624
申请日：2006-05-04
申请人： Lewis Nardini , Alan D. Hales
发明人： Lewis Nardini , Alan D. Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This technique supplies a predefined pattern to parallel scan chains following power-on reset. The predefined pattern places the device or module in a architecturally specified reset state. The parallel scan chains are required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits.
摘要翻译：扫描顺序初始化技术将预定义的开机状态提供给设备或模块，而不使用对寄存器的显式复位输入。上电复位后，这种技术为并行扫描链提供预定义的模式。预定义模式将设备或模块置于架构上指定的复位状态。并行扫描链是结构制造测试所必需的。一旦上电复位扫描完成，上电复位定序器就会指示完成其他电路的状态初始化。

32. 发明授权

US07383367B2 Progressive extended compression mask for dynamic trace 有权
标题翻译：逐行扩展压缩掩码，用于动态跟踪
公开(公告)号：US07383367B2
公开(公告)日：2008-06-03
申请号：US11566757
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored prior trace address. Only the least significant bytes of the current trace address that do not match the stored prior trace address or are less significant than any section of the current trace address that does not match the stored prior trace address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The prior trace address may be updated with the current trace address if there is a complete mismatch.
摘要翻译：本发明通过将当前跟踪地址的各个字节与存储的先前跟踪地址进行比较来提供跟踪地址压缩。只有当前跟踪地址中与存储的先前跟踪地址不匹配或者比当前跟踪地址中与存储的先前跟踪地址不匹配的任何部分不太重要的最低有效字节被传送。这有时会减少需要传输的数据量。如果存在完全不匹配，则可以使用当前跟踪地址更新先前的跟踪地址。

33. 发明申请

US20070294590A1 COMPRESSION SCHEME TO REDUCE THE BANDWIDTH REQUIREMENTS FOR CONTINUOUS TRACE STREAM ENCODING OF SYSTEM PERFORMANCE 审中-公开
标题翻译：压缩方案，以减少系统性能连续跟踪编码的带宽要求
公开(公告)号：US20070294590A1
公开(公告)日：2007-12-20
申请号：US11383697
申请日：2006-05-16
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F11/00
CPC分类号： G06F11/26
摘要： A system and method of counting event patterns in order to reduce the bandwidth of event data sent to a monitoring computer. The event patterns are output as one or more data packets indicating the event pattern and a number of occurrences of the pattern.
摘要翻译：计数事件模式的系统和方法，以减少发送到监控计算机的事件数据的带宽。事件模式作为一个或多个数据分组输出，指示事件模式和模式的出现次数。

34. 发明申请

US20060259838A1 Scan Sequenced Power-On Initialization 有权
标题翻译：扫描顺序上电初始化
公开(公告)号：US20060259838A1
公开(公告)日：2006-11-16
申请号：US11381624
申请日：2006-05-04
申请人： Lewis Nardini , Alan Hales
发明人： Lewis Nardini , Alan Hales
IPC分类号： G01R31/28
CPC分类号： G01R31/318575
摘要： A scan sequenced initialization technique supplies a predefined power-on state to a device or module without using explicit reset input to the registers. This invention supplies a predefined pattern to parallel scan chains following power-on reset. These parallel scan chains are already required for structural manufacturing test. Once the power-on reset scanning is complete, the power-on reset sequencer indicates completion of state initialization to other circuits. These other circuits are those which interact with the module or device using this invention.
摘要翻译：扫描顺序初始化技术将预定义的开机状态提供给设备或模块，而不使用对寄存器的显式复位输入。本发明在上电复位后将预定义的模式提供给并行扫描链。这些平行扫描链已经是结构制造测试所必需的。一旦上电复位扫描完成，上电复位定序器就会指示完成其他电路的状态初始化。这些其他电路是与使用本发明的模块或装置相互作用的电路。

35. 发明授权

US07047451B2 Tracing program counter addresses using native program counter format and instruction count format 有权
标题翻译：使用本地程序计数器格式和指令计数格式跟踪程序计数器地址
公开(公告)号：US07047451B2
公开(公告)日：2006-05-16
申请号：US10302025
申请日：2002-11-22
申请人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
发明人： Manisha Agarwala , Bryan Thome , John M. Johnsen , Gary L. Swoboda , Lewis Nardini , Maria B. H. Gill
IPC分类号： G06F11/00
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing program counter activity in a data processor periodically transmits a program counter sync point including the current program counter address. Between sync points the program counter address is indicated by a program counter offset relative to the last program counter sync point. The program counter offset is sent as integral number of sections of a predetermined number of bits. Program counter sync points are transmitted often enough so that the program counter offset requires at most one less section than the program counter address.
摘要翻译：在数据处理器中跟踪程序计数器活动的方法周期性地发送包括当前程序计数器地址的程序计数器同步点。在同步点之间，程序计数器地址由相对于最后一个程序计数器同步点的程序计数器偏移指示。程序计数器偏移作为整数个预定位数的部分发送。程序计数器的同步点经常被传送到足够多的程序计数器偏移量至少比程序计数器地址少一个部分。

36. 发明授权

US07047270B2 Reporting a saturated counter value 有权
标题翻译：报告饱和计数器值
公开(公告)号：US07047270B2
公开(公告)日：2006-05-16
申请号：US10301897
申请日：2002-11-22
申请人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
发明人： Manisha Agarwala , John M. Johnsen , Lewis Nardini
IPC分类号： G06F7/38
CPC分类号： G06F11/261
摘要： A saturating count counts received event signals up to a first predetermined number. An overflow counter counts overflows up to a second predetermined number. The counter indicates overflow when the overflow count is non-zero and saturates and stops counting at a maximum count when the overflow count reaches the second predetermined number. The counter can be read via a register read operation. The sum of the sum of the first predetermined number of bits and the second predetermined number of bits being an integral multiple of 8 bits.
摘要翻译：饱和计数将接收的事件信号计数到第一预定数量。溢出计数器计数溢出到第二预定数量。当溢出计数达到第二个预定数量时，计数器指示溢出计数不为零并饱和，并以最大计数停止计数。可以通过寄存器读取操作读取计数器。第一预定位数和第二预定位数之和为8位的整数倍的总和。

37. 发明授权

US06829696B1 Data processing system with register store/load utilizing data packing/unpacking 有权
标题翻译：数据处理系统，具有使用数据打包/打包的寄存器存储/负载
公开(公告)号：US06829696B1
公开(公告)日：2004-12-07
申请号：US09687540
申请日：2000-10-13
申请人： Keith Balmer , Karl M. Guttag , Lewis Nardini
发明人： Keith Balmer , Karl M. Guttag , Lewis Nardini
IPC分类号： G06F9312
CPC分类号： G06F9/30043 , G06F9/30032 , G06F9/30036 , G06F9/345 , G06F9/3824 , G06F9/3828 , G06F9/3853
摘要： A data processing system (e.g., microprocessor 30) for packing register data while storing it to memory and unpacking data read from memory while loading it into registers using single processor instructions. The system comprises a memory (42) and a central processing unit core (44) with at least one register file (76). The core is responsive to a load instruction (e.g., LDW_BH[U] instruction 184) to retrieve at least one data word from memory and parse the data word over selected parts of at least two data registers in the register file. The core is responsive to a store instruction (e.g., STBH_W instruction 198) to concatenate data from selected parts of at least two data registers into at least one data word and save the data word to memory. The number of data registers is greater than the number of data words parsed into or concatenated from the data registers. Both memory storage space and central processor unit resources are utilized efficiently when working with packed data. A single store or load instruction can perform all of the tasks that used to take several instructions, while at the same time conserving memory space.
摘要翻译：数据处理系统（例如，微处理器30），用于打包寄存器数据，同时将其存储到存储器并且解包从存储器读取的数据，同时使用单个处理器指令将其加载到寄存器中。该系统包括具有至少一个寄存器文件（76）的存储器（42）和中央处理单元核心（44）。核心响应于加载指令（例如LDW_BH [U]指令184））从存储器检索至少一个数据字，并且通过寄存器文件中的至少两个数据寄存器的选定部分解析数据字。核心响应于存储指令（例如，STBH_W指令198）将从至少两个数据寄存器的所选部分的数据连接到至少一个数据字中并将数据字保存到存储器。数据寄存器的数量大于从数据寄存器解析或级联的数据字数。当处理打包数据时，存储器存储空间和中央处理器单元资源都被有效利用。单个存储或加载指令可以执行用于执行多个指令的所有任务，同时节省内存空间。

38. 发明授权

US07562170B2 Programmable extended compression mask for dynamic trace 有权
公开(公告)号：US07562170B2
公开(公告)日：2009-07-14
申请号：US11566762
申请日：2006-12-05
申请人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
发明人： Lewis Nardini , Manisha Agarwala , John M. Johnsen
IPC分类号： G06F3/00 , G06F13/12 , G06F9/455 , G06R31/28
CPC分类号： G06F11/3636 , G06F11/3476
摘要： This invention provides trace address compression by comparing respective bytes of a current trace address with a stored comparison address. Only the least significant bytes of the current trace address that do not match the comparison address or are less significant than any section of the current trace address that does not match the comparison address are transmitted. This sometimes reduces the amount of data that needs to be transmitted. The comparison address is specified by a central processing unit via a memory mapped register write operation.

39. 发明申请

US20080068238A1 Entry/Exit Control To/From a Low Power State in a CPU with an Unprotected Pipeline 审中-公开
标题翻译：在具有无保护管道的CPU中进入/退出控制到低功耗状态
公开(公告)号：US20080068238A1
公开(公告)日：2008-03-20
申请号：US11855585
申请日：2007-09-14
申请人： David Bell , Timothy Anderson , Lewis Nardini , Jose Flores , Anthony Lell
发明人： David Bell , Timothy Anderson , Lewis Nardini , Jose Flores , Anthony Lell
IPC分类号： H03M1/00
CPC分类号： G06F1/3203 , G06F1/3243 , Y02D10/152 , Y02D50/20
摘要： An embedded megamodule and an embedded CPU enable power-saving through a combination of hardware and software. The CPU configures the power-down controller (PDC) logic within megamodule and can software trigger a low-power state of logic blocks and memory during processor IDLE periods. To wake from this power-down state, a system event is asserted to the CPU through the module interrupt controller. Thus the entry into a low-power state is software-driven during periods of inactivity and power restoration is on system activity that demands the attention of the CPU.
摘要翻译：嵌入式巨型模块和嵌入式CPU通过硬件和软件的组合实现节能。 CPU在兆模块内配置掉电控制器（PDC）逻辑，并且可以在处理器空闲周期期间软件触发逻辑块和存储器的低功耗状态。要从此掉电状态唤醒，系统事件将通过模块中断控制器发送到CPU。因此，进入低功耗状态是在非活动期间进行软件驱动，并且电源恢复是需要CPU注意的系统活动。

40. 发明申请

US20070255935A1 Tracing through reset 有权
公开(公告)号：US20070255935A1
公开(公告)日：2007-11-01
申请号：US11820546
申请日：2007-06-20
申请人： Manisha Agarwala , Lewis Nardini
发明人： Manisha Agarwala , Lewis Nardini
IPC分类号： G06F15/177
CPC分类号： G06F11/3636 , G06F11/3656
摘要： A method of tracing a data processor upon reset of the data processor. A data processor reset signal resets the data processor, part of trace collection hardware and does not reset remaining parts of trace collection hardware. The data processor reset signal may be not owned, owned by an application program or owned by a debugger. The partial not reset of the trace collection hardware occurs only upon a data processor reset signal owned by the debugger. A trace logic reset signal resets both the data processor and the trace collection hardware when not owned. This trace logic reset signal resets the data processor only when owned by the debugger and resets the trace collection hardware when owned by an application program.

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