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31. 发明授权

US07144766B2 Method of manufacturing semiconductor integrated circuit device having polymetal gate electrode 有权
标题翻译：具有多金属栅电极的半导体集成电路器件的制造方法
公开(公告)号：US07144766B2
公开(公告)日：2006-12-05
申请号：US11198858
申请日：2005-08-08
申请人： Naoki Yamamoto , Hiroyuki Uchiyama , Norio Suzuki , Eisuke Nishitani , Shin'ichiro Kimura , Kazuyuki Hozawa
发明人： Naoki Yamamoto , Hiroyuki Uchiyama , Norio Suzuki , Eisuke Nishitani , Shin'ichiro Kimura , Kazuyuki Hozawa
IPC分类号： H01L22/336 , H01L22/8234
CPC分类号： H01L21/28194 , H01L21/02057 , H01L21/02068 , H01L21/02071 , H01L21/0217 , H01L21/02211 , H01L21/0223 , H01L21/02238 , H01L21/02255 , H01L21/02271 , H01L21/28061 , H01L21/28176 , H01L21/28247 , H01L21/31662 , H01L21/67115 , H01L21/76838 , H01L21/823437 , H01L21/84 , H01L27/10814 , H01L27/10873 , H01L27/10894 , H01L27/1214 , H01L29/4941 , H01L29/518
摘要： When an oxidation treatment for regenerating a gate insulating film 6 is performed after forming gate electrodes 7A of a polymetal structure in which a WNx film and a W film are stacked on a polysilicon film, a wafer 1 is heated and cooled under conditions for reducing a W oxide 27 on the sidewall of each gate electrode 7A. As a result, the amount of the W oxide 27 to be deposited on the surface of the wafer 1 is reduced.
摘要翻译：当在多晶硅膜上堆叠WN薄膜和W膜的多金属结构的栅极电极7A之后进行用于再生栅极绝缘膜6的氧化处理时，晶片1 在用于还原每个栅电极7A的侧壁上的W氧化物27的条件下被加热和冷却。结果，沉积在晶片1的表面上的W氧化物27的量减少。

32. 发明申请

US20060097314A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060097314A1
公开(公告)日：2006-05-11
申请号：US11264092
申请日：2005-11-02
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L29/94
CPC分类号： H01L27/10891 , H01L21/28061 , H01L27/10855 , H01L27/10876 , H01L27/10888 , H01L29/66621 , H01L29/7834
摘要： After an element isolation region is formed using a field-forming silicon nitride film, the silicon nitride film and a semiconductor substrate are patterned. Thereafter, the silicon nitride film and the semiconductor substrate are patterned, thereby forming a gate trench reaching the semiconductor substrate in an active region. Next, after a gate electrode is formed within a gate trench, the silicon nitride film is removed, thereby forming a contact hole. A contact plug is buried into this contact hole. Accordingly, a diffusion layer contact pattern becomes unnecessary, and the active region can be reduced. Because a gate electrode is buried in the gate trench, a gate length is increased, and a sub-threshold current can be reduced.
摘要翻译：在使用场致发射氮化硅膜形成元件隔离区之后，对氮化硅膜和半导体衬底进行图案化。此后，对氮化硅膜和半导体衬底进行构图，从而在活性区域形成到达半导体衬底的栅极沟槽。接下来，在栅极沟槽中形成栅电极之后，去除氮化硅膜，从而形成接触孔。接触塞被埋入该接触孔中。因此，不需要扩散层接触图案，可以减少有源区域。因为栅电极被埋在栅极沟槽中，栅极长度增加，并且可以减小次级阈值电流。

33. 发明申请

US20060091454A1 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US20060091454A1
公开(公告)日：2006-05-04
申请号：US11249400
申请日：2005-10-14
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L29/94
CPC分类号： H01L29/66583 , H01L27/10855 , H01L27/10873 , H01L27/10888 , H01L27/10891 , H01L29/66553
摘要： After an isolation region is formed using a field-forming silicon nitride film, this silicon nitride film is patterned, thereby a gate trench is formed. Next, a gate electrode material is buried into the gate trench, and this is etched back. Thereafter, the silicon nitride is removed, thereby a contact hole is formed. A contact plug is buried into this contact hole. With this arrangement, the contact plug can be formed without using a diffusion layer contact pattern. At the same time, the periphery of the contact plug substantially coincides with a boundary between the element isolation region and the active region. Accordingly, the active region can be reduced.
摘要翻译：在使用场致发射氮化硅膜形成隔离区之后，对该氮化硅膜进行构图，从而形成栅极沟槽。接下来，将栅极电极材料埋入栅极沟槽中，并将其蚀刻回来。此后，除去氮化硅，从而形成接触孔。接触塞被埋入该接触孔中。通过这种布置，可以在不使用扩散层接触图案的情况下形成接触插塞。同时，接触插塞的周边基本上与元件隔离区域和有源区域之间的边界一致。因此，能够减少有源区域。

34. 发明申请

US20060081879A1 Semiconductor device and a manufacturing method thereof, and semiconductor module 失效
标题翻译：半导体装置及其制造方法以及半导体模块
公开(公告)号：US20060081879A1
公开(公告)日：2006-04-20
申请号：US11247234
申请日：2005-10-12
申请人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
发明人： Kenichi Tanaka , Hidetoshi Matsumoto , Isao Ohbu , Kazuhiro Mochizuki , Tomonori Tanoue , Chisaki Takubo , Hiroyuki Uchiyama
IPC分类号： H01L31/109
CPC分类号： H01L23/482 , H01L24/48 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014 , H01L2924/01078 , H01L2924/01079 , H01L2924/09701 , H01L2924/12041 , H01L2924/1305 , H01L2924/14 , H01L2924/1423 , H01L2924/16152 , H01L2924/19041 , H01L2924/30107 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： The present invention provides a semiconductor device which comprises active components, passive components, wiring lines and electrodes and are satisfactory in terms of mechanical strength, miniaturization and thermal stability. In the semiconductor device, openings are formed just below active components. These openings are filled with conductor layers. Conductor layers are also formed where openings are not formed.
摘要翻译：本发明提供一种半导体器件，其包括有源部件，无源部件，布线和电极，并且在机械强度，小型化和热稳定性方面令人满意。在半导体器件中，开口形成在活性部件的正下方。这些开口填充有导体层。还形成了未形成开口的导体层。

35. 发明授权

US06809479B2 Self-ballasted electrodeless discharge lamp and electrodeless discharge lamp operating device 失效
标题翻译：自镇流无电极放电灯和无电极放电灯操作装置
公开(公告)号：US06809479B2
公开(公告)日：2004-10-26
申请号：US10265047
申请日：2002-10-04
申请人： Yoko Shimomura , Koji Miyazaki , Satoshi Kominami , Kohei Enchi , Hiroyuki Uchiyama
发明人： Yoko Shimomura , Koji Miyazaki , Satoshi Kominami , Kohei Enchi , Hiroyuki Uchiyama
IPC分类号： H05B4116
CPC分类号： H01J65/048
摘要： A self-ballasted electrodeless discharge lamp of the invention is provided with a discharge vessel filled with discharge gas, the discharge vessel having a cavity portion, a coil inserted into the cavity portion of the discharge vessel, a ballast circuit for supplying high frequency power to the coil, and a lamp base that is electrically connected to the ballast circuit, wherein the discharge vessel, the coil, the ballast circuit, and the lamp base are configured as a single unit, and a reflective tape for reflecting light that is radiated from the discharge gas and emitted from inside the discharge vessel to its cavity portion side is wound around the coil.
摘要翻译：本发明的自镇流无电极放电灯设置有充满放电气体的放电容器，放电容器具有空腔部分，插入放电容器的空腔部分中的线圈，用于将高频电力提供给线圈和电连接到镇流器电路的灯座，其中放电容器，线圈，镇流器电路和灯座被配置为单个单元，以及用于反射从第放电气体从放电容器内部排出到其空腔部侧卷绕在线圈上。

36. 发明授权

US06583049B2 Semiconductor integrated circuit device and method for making the same 失效
公开(公告)号：US06583049B2
公开(公告)日：2003-06-24
申请号：US09998644
申请日：2001-12-03
申请人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
发明人： Masayuki Suzuki , Shinji Nishihara , Masashi Sahara , Shinichi Ishida , Hiromi Abe , Sonoko Tohda , Hiroyuki Uchiyama , Hideaki Tsugane , Yoshiaki Yoshiura
IPC分类号： H01L214763
CPC分类号： H01L21/76862 , H01L21/32051 , H01L21/7684 , H01L21/76841 , H01L21/76843 , H01L21/76849 , H01L21/7685 , H01L23/53223 , H01L23/53266 , H01L24/03 , H01L24/05 , H01L24/11 , H01L24/45 , H01L24/48 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/05082 , H01L2224/05083 , H01L2224/05124 , H01L2224/05166 , H01L2224/05184 , H01L2224/05187 , H01L2224/05624 , H01L2224/13099 , H01L2224/45144 , H01L2224/48463 , H01L2224/48624 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01015 , H01L2924/01018 , H01L2924/01019 , H01L2924/01022 , H01L2924/01029 , H01L2924/0104 , H01L2924/0105 , H01L2924/01074 , H01L2924/01075 , H01L2924/01079 , H01L2924/04941 , H01L2924/05042 , H01L2924/14 , H01L2924/00014 , H01L2924/01007 , H01L2924/04953 , H01L2924/00
摘要： A method for making a semiconductor integrated circuit device comprises the steps of: (a) depositing a first underlying film made of titanium nitride, on an insulating film having a plurality of through-holes; (b) depositing a tungsten film on the first underlying film, and etching the tungsten film back by means of a fluorine-containing plasma thereby leaving the tungsten film only in the connection holes; (c) sputter etching the surface of the first underlying film to remove the fluorine from the surface of the first underlying film; and (d) forming an aluminum film on the first underlying film. The semiconductor integrated circuit device obtained by the method is also described.

37. 发明授权

US5885990A Substituted amidinonaphthyl ester derivative 失效
标题翻译：取代的脒基萘酯衍生物
公开(公告)号：US5885990A
公开(公告)日：1999-03-23
申请号：US849761
申请日：1997-06-12
申请人： Toyoo Nakayama , Hiroyuki Kawamura , Hiroyuki Uchiyama
发明人： Toyoo Nakayama , Hiroyuki Kawamura , Hiroyuki Uchiyama
IPC分类号： C07C257/18 , C07C279/18 , C07D233/50 , C07D277/18 , C07D295/13 , C07D295/155 , C07D295/28 , A61K31/245 , C07D233/24 , C07D295/14
CPC分类号： C07D295/32 , C07C257/18 , C07C279/18 , C07D233/50 , C07D277/18 , C07D295/13 , C07D295/155
摘要： Substituted amidinonaphthyl ester compounds effective for treatment of thrombosis are represented by the following formula (I) and pharmaceutically acceptable acid addition salts thereof: ##STR1## wherein R.sub.1 represents (4,5-dihydro-1H-imidazol-2-yl)amino group, (4,5-dihydro-1,3-thiazol-2-yl)amino group, amidino group, morpholinomethyl group, nitro group, amino group, dimethylamino group, ##STR2## R.sub.3 represents hydrogen, methoxy group, hydroxyl group, acetylamino group, morpholino group, piperidino group, 1-pyrrolidinyl group or dimethylamino group,m represents 0-4,R.sub.4 represents hydrogen or methyl group,R.sub.2 represents NH.sub.2 CO(CH.sub.2).sub.n --, 2-(carbamoyl)vinyl group or R.sub.5 OOC(CH.sub.2).sub.n --,R.sub.5 represents dimethylcarbamoylmethyl group, hydrogen or lower alkyl group, andn represents 0-2.
摘要翻译： PCT No.PCT / JP95 / 02723 Sec。 371日期：1997年6月12日 102（e）日期1997年6月12日PCT 1995年12月27日PCT PCT。公开号WO96 / 20917 日期：1996年7月11日有效治疗血栓形成的取代脒基萘酯化合物由下式（I）及其药学上可接受的酸加成盐表示：其中R1表示（4,5-二氢-1H-咪唑 -2-基）氨基，（4,5-二氢-1,3-噻唑-2-基）氨基，脒基，吗啉代甲基，硝基，氨基，二甲基氨基，R 3表示氢，甲氧基，羟基，乙酰氨基，吗啉代基，哌啶子基，1-吡咯烷基或二甲基氨基，m表示0-4，R4表示氢或甲基，R2表示NH2CO（CH2）n-，2-（氨基甲酰基）乙烯基或R5OOC（CH2）n-，R5代表二甲基氨基甲酰基甲基，氢或低级烷基，n代表0-2。

38. 发明授权

US5217917A Semiconductor memory device with improved substrate arrangement to permit forming a plurality of different types of random access memory, and a testing method therefor 失效
标题翻译：具有改进的基板布置以允许形成多种不同类型的随机存取存储器的半导体存储器件及其测试方法
公开(公告)号：US5217917A
公开(公告)日：1993-06-08
申请号：US496280
申请日：1990-03-20
申请人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
发明人： Yasushi Takahashi , Hidetoshi Iwai , Satoshi Oguchi , Hisashi Nakamura , Hiroyuki Uchiyama , Toshitugu Takemuma , Shigetoshi Sakomura , Kazuyuki Miyazawa , Masamichi Ishihara , Ryoichi Hori , Takeshi Kizaki , Yoshihisa Koyama , Haruo Ii , Masaya Muranaka , Hidetomo Aoyagi , Hiromi Matsuura
IPC分类号： G11C5/00 , G11C5/02 , G11C7/10 , G11C11/4074 , G11C11/408 , G11C11/4096 , G11C29/00 , G11C29/02 , G11C29/46 , G11C29/50
CPC分类号： G11C29/027 , G11C11/4074 , G11C11/4082 , G11C11/4096 , G11C29/02 , G11C29/46 , G11C29/50 , G11C29/50012 , G11C5/00 , G11C5/025 , G11C7/1045 , G11C11/401 , G11C2029/5006 , G11C29/78
摘要： A semiconductor memory device is provided which includes a substrate arrangement which is suitable for forming a large number of types of DRAMs having different package specifications, different bit structure and different operating modes. In conjunction with this, the bonding pads are arranged at optimum locations for accommodating the different package types. Various layout arrangements are also provided to minimize space and to improve access time. Additional features are provided, including improved output buffer circuitry, protection circuitry and testing methods to facilitate operation of the semiconductor memory device.
摘要翻译：提供了一种半导体存储器件，其包括适于形成具有不同封装规格，不同位结构和不同工作模式的大量类型的DRAM的衬底布置。结合这些，接合垫被布置在适于不同包装类型的最佳位置处。还提供了各种布局布置以最小化空间并改善访问时间。提供了额外的功能，包括改进的输出缓冲器电路，保护电路和测试方法以便于半导体存储器件的操作。

39. 发明授权

US08969935B2 Semiconductor memory device having plural cell capacitors stacked on one another and manufacturing method thereof 有权
标题翻译：具有彼此堆叠的多个电池电容器的半导体存储器件及其制造方法
公开(公告)号：US08969935B2
公开(公告)日：2015-03-03
申请号：US13439423
申请日：2012-04-04
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： H01L27/108 , H01L49/02
CPC分类号： H01L27/10814 , H01L27/10817 , H01L28/86 , H01L28/90
摘要： Disclosed herein is a device that includes a semiconductor substrate having a first area, a plurality of cell transistors arranged on the first area of the semiconductor substrate, and a plurality of cell capacitors each coupled to an associated one of the cell transistors, the cell capacitors being provided so as to overlap with one another on the first area.
摘要翻译：本文公开了一种器件，其包括具有第一区域的半导体衬底和布置在半导体衬底的第一区域上的多个单元晶体管，以及多个单元电容器，每个单元电容器耦合到相关联的一个单元晶体管，单元电容器被设置为在第一区域上彼此重叠。

40. 发明授权

US07724272B2 Print unit 失效
标题翻译：打印单位
公开(公告)号：US07724272B2
公开(公告)日：2010-05-25
申请号：US12207100
申请日：2008-09-09
申请人： Hiroyuki Uchiyama
发明人： Hiroyuki Uchiyama
IPC分类号： B41J2/44 , G03B17/24
CPC分类号： H04N1/00257 , H04N1/00249 , H04N2201/0082 , H04N2201/0084 , H04N2201/0089
摘要： A print unit for transferring an image to a photosensitive medium is provided, and the print unit includes an intercepting member for intercepting light; a first plane light-emitting member for forming a first image by emitting light, provided on one side of the intercepting member; a second plane light-emitting member for forming a second image by emitting light, provided on the other side of the intercepting member; and a control unit for controlling light-emission of the first and second surface emitting members and transferring at least one or more of images to the photosensitive medium.
摘要翻译：提供了用于将图像转印到感光介质的打印单元，并且打印单元包括用于遮挡光的遮挡构件; 用于通过发射光形成第一图像的第一平面发光部件，设置在所述拦截部件的一侧; 用于通过发射光形成第二图像的第二平面发光部件，设置在所述拦截部件的另一侧; 以及控制单元，用于控制第一和第二表面发射构件的发光并将至少一个或多个图像转印到感光介质。

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