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31. 发明授权

US06521161B1 Method for manufacturing a golf ball 有权
标题翻译：制造高尔夫球的方法
公开(公告)号：US06521161B1
公开(公告)日：2003-02-18
申请号：US09476365
申请日：2000-01-03
申请人： Takayuki Tanaka , Naoki Baba , Hiroaki Tanaka , Hiroshi Hirata
发明人： Takayuki Tanaka , Naoki Baba , Hiroaki Tanaka , Hiroshi Hirata
IPC分类号： B29C4318
CPC分类号： B29C43/36 , A63B37/0003 , A63B37/005 , A63B45/00 , B29C33/0022 , B29C33/0055 , B29C35/02 , B29C37/0003 , B29C37/005 , B29C43/021 , B29C43/52 , B29C2043/3488 , B29K2021/00 , B29L2031/54 , B29L2031/545 , B29L2031/772
摘要： A manufacturing method for an one-piece ball formed with vulcanization in which a partial mold has eight grooves in a radius direction of a mating face, and ends of spews generated when the vulcanization is conducted do not connect and unify one another.
摘要翻译：一种用硫化形成的一体式球的制造方法，其中部分模具在配合面的半径方向上具有八个凹槽，并且在进行硫化时产生的喷嘴的末端不彼此连接和一体化。

32. 发明授权

US5446694A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US5446694A
公开(公告)日：1995-08-29
申请号：US225968
申请日：1994-04-08
申请人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
发明人： Takayuki Tanaka , Junichi Suyama , Kazukiyo Fukudome , Yuki Hashimoto
IPC分类号： G11C11/407 , G11C5/14 , G11C11/4074 , G11C11/409 , G11C11/4091 , G11C11/34
CPC分类号： G11C5/147 , G11C11/4074 , G11C11/4091
摘要： A semiconductor memory device of the present invention comprises an internal power supplying circuit electrically connected to an external power supply having an external source potential and for supplying an internal potential lower than the external source potential, a precharging circuit for supplying a half potential of the internal potential to each of memory cells and bit lines, and a switching circuit electrically connected between each bit line and the precharging circuit and controlled based on an equalize signal output from a control circuit and having the same potential as the external source potential. The semiconductor memory device of such a type that even if a potential on each bit line increases excessively, such a potential does not exert an influence on each memory cell, can be realized owing to the above structure.
摘要翻译：本发明的半导体存储器件包括：内部供电电路，其电连接到具有外部源极电位的外部电源，并提供低于外部电位电位的内部电位;预充电电路，用于提供内部电位的半电位每个存储单元和位线的电位，以及电连接在每个位线和预充电电路之间的开关电路，并且基于从控制电路输出并具有与外部源极电位相同的电位的均衡信号来控制。这种类型的半导体存储器件，即使每个位线上的电位都过大，这种电位也不会对每个存储单元产生影响，所以可以通过上述结构实现。

33. 发明授权

US5444662A Dynamic random access memory with bit line equalizing means 失效
标题翻译：具有位线均衡装置的动态随机存取存储器
公开(公告)号：US5444662A
公开(公告)日：1995-08-22
申请号：US257450
申请日：1994-06-08
申请人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
发明人： Takayuki Tanaka , Yoshimasa Sekino , Yoshihiro Murashima , Yasuhiro Tokunaga , Joji Ueno , Takeru Yonaga
IPC分类号： G11C11/409 , G11C11/4094 , G11C7/00
CPC分类号： G11C11/4094
摘要： A dynamic random access memory of the complementary MOS transistor type has memory cells connected between complementary bit lines on one side of a pair of transfer gates and a sense amplifier connected to nodes on the other side of the transfer gates, so that the sense amplifier can be connected to the bit lines and memory cells through the pair of transfer gates. A sense amplifier equalizing circuit and a bit line equalizing circuit are provided on opposite sides of the transfer gates so that the potentials on the bit lines can be equalized independently of equalization of the potentials on the nodes. Accordingly, there is no delay in the equalization due to the transfer gates connecting the nodes to the bit lines. According to another aspect of the invention, the transfer gates each include a pair of MOSFET transistors connected to each other in parallel, wherein one transistor of each pair of MOSFET transistors is an n-channel MOSFET transistor and the other transistor of each pair of MOSFET transistors is a p-channel MOSFET transistor. By, for example, connecting the gate of the NMOS transistor of each transfer to the power source and connecting the gate of each PMOS transistor to the ground, it is possible to prevent erroneous operation of the DRAM from a drop in the gate potential.
摘要翻译：互补MOS晶体管类型的动态随机存取存储器具有连接在一对传输门的一侧上的互补位线和连接到传输门的另一侧上的节点的读出放大器之间的存储单元，使得读出放大器可以通过一对传输门连接到位线和存储单元。感测放大器均衡电路和位线均衡电路设置在传输门的相对侧上，使得可以独立于节点上的电位的均衡来均衡位线上的电位。因此，由于将节点连接到位线的传输门，所以均衡没有延迟。根据本发明的另一方面，传输门每个包括彼此并联连接的一对MOSFET晶体管，其中每对MOSFET晶体管中的一个晶体管是n沟道MOSFET晶体管，并且每对MOSFET的另一个晶体管晶体管是一个p沟道MOSFET晶体管。例如，通过将每个传输的NMOS晶体管的栅极连接到电源并将每个PMOS晶体管的栅极连接到地，可以防止DRAM的错误操作从栅极电位的下降。

34. 发明授权

US5258873A Image-reading device 失效
标题翻译：图像读取装置
公开(公告)号：US5258873A
公开(公告)日：1993-11-02
申请号：US865267
申请日：1992-04-08
申请人： Yoshihiko Mishina , Masaaki Oda , Yutaka Yamamoto , Takayuki Tanaka
发明人： Yoshihiko Mishina , Masaaki Oda , Yutaka Yamamoto , Takayuki Tanaka
IPC分类号： G02B3/00 , G02B7/02 , H04N1/031
CPC分类号： G02B3/0087 , G02B3/005 , G02B3/0075 , G02B7/02 , H04N1/0312 , H04N1/0315 , H04N1/0318 , H04N2201/02404 , H04N2201/02452 , H04N2201/03112 , H04N2201/0315
摘要： An image-reading device comprises a lens unit array comprising an array of distributed refractive index plastic cylindrical lens elements and plastic plates, adhering the distributed refractive index plastic cylindrical lens elements therebetween, and a plastic case containing and holding the lens unit array. The difference in the thermal expansion coefficients of the plates of the lens unit array and the plastic case is 5.0.times.10.sup.-5 cm/cm/.degree. C. or below, or more preferably, 3.0.times.10.sup.-5 cm/cm/.degree. C. or below. The plastic case is formed by connecting, in a longitudinal arrangement, a plurality of case segments formed by an injection molding.
摘要翻译：图像读取装置包括透镜单元阵列，该透镜单元阵列包括分布折射率的塑料柱面透镜元件和塑料板的阵列，将分布的折射率塑料柱面透镜元件粘附在其间，以及容纳和保持透镜单元阵列的塑料壳体。透镜单元阵列和塑料壳体的板的热膨胀系数的差为5.0×10 -5 cm / cm /℃以下，更优选为3.0×10 -5 cm / cm /℃，或下面。塑料外壳是通过纵向配置连接多个通过注模成型形成的外壳段形成的。

35. 发明授权

US09425070B2 Semiconductor device and a method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09425070B2
公开(公告)日：2016-08-23
申请号：US13005841
申请日：2011-01-13
申请人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Kana Nagayoshi , Takuya Nakamura
发明人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Kana Nagayoshi , Takuya Nakamura
IPC分类号： H01L23/48 , H01L21/56
CPC分类号： H01L21/563 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip.
摘要翻译：这里公开了一种半导体器件，包括：安装体，其具有形成布线图案的第一主表面; 半导体芯片安装在其上形成有布线图案的安装体的主表面上方; 填充在安装体和半导体芯片之间的底部填充材料，从而在半导体芯片的外周部分形成圆角; 以及引导部，其形成在所述圆角部分的外侧，所述边缘沿着所述边缘形成为最长，在安装有所述半导体芯片的所述安装体上测量芯片安装面积的四个侧部，所述引入部分服务以在底座和半导体芯片之间引入底部填充材料。

36. 发明授权

US08673647B2 Stress evaluating apparatus, method, system and program and recording medium therefor 有权
标题翻译：应力评估装置，方法，系统及程序及记录介质
公开(公告)号：US08673647B2
公开(公告)日：2014-03-18
申请号：US12365270
申请日：2009-02-04
申请人： Takayuki Tanaka , Yukio Nihei , Toshihiko Ando , Minoru Yamakado , Keita Takamatsu , Eiko Takahashi , Norio Sasamori
发明人： Takayuki Tanaka , Yukio Nihei , Toshihiko Ando , Minoru Yamakado , Keita Takamatsu , Eiko Takahashi , Norio Sasamori
IPC分类号： G01N33/00
CPC分类号： G01N33/6812 , G01N2800/304 , G06F19/18 , G06F19/24 , G06F19/28
摘要： According to the method of evaluating stress of the present invention, amino acid concentration data on the concentration value of amino acid in blood collected from a subject to be evaluated is measured, and a stress state including at least depressive illness and major depressive illness in the subject is evaluated based on the concentration value of at least one of Lys, His, ABA, Asn, Phe, Leu, Ile, Val, Trp, Tyr and Met contained in the measured amino acid concentration data of the subject.
摘要翻译：根据本发明的应力评价方法，测定从评价对象收集的血液中的氨基酸浓度值的氨基酸浓度数据，并且测定包含至少抑郁症和重度抑郁症的应激状态基于测定的受试者的氨基酸浓度数据中所含的Lys，His，ABA，Asn，Phe，Leu，Ile，Val，Trp，Tyr和Met中的至少一种的浓度值进行评估。

37. 发明申请

US20110175239A1 SEMICONDUCTOR DEVICE AND A METHOD OF MANUFACTURING THE SAME 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20110175239A1
公开(公告)日：2011-07-21
申请号：US13005841
申请日：2011-01-13
申请人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Kana Nagayoshi , Takuya Nakamura
发明人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Kana Nagayoshi , Takuya Nakamura
IPC分类号： H01L23/48 , H01L21/50
CPC分类号： H01L21/563 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： Disclosed herein is a semiconductor device, including: a mount body having a first principal surface on which a wiring pattern is formed; a semiconductor chip mounted above the principal surface of the mount body on which the wiring pattern is formed; an underfill material filled between the mount body and the semiconductor chip, thereby forming a fillet in an outer peripheral portion of the semiconductor chip; and an introduction portion formed outside a side portion, along which the fillet is formed so as to be longest, of four side portions which measure a chip mounting area, on the mount body, onto which the semiconductor chip is mounted, the introduction portion serving to introduce the underfill material between the mount body and the semiconductor chip.
摘要翻译：这里公开了一种半导体器件，包括：安装体，其具有形成布线图案的第一主表面; 半导体芯片安装在其上形成有布线图案的安装体的主表面上方; 填充在安装体和半导体芯片之间的底部填充材料，从而在半导体芯片的外周部分形成圆角; 以及引导部，其形成在所述圆角部分的外侧，所述边缘沿着所述边缘形成为最长，在安装有所述半导体芯片的所述安装体上测量芯片安装面积的四个侧部，所述引入部分服务以在底座和半导体芯片之间引入底部填充材料。

38. 发明申请

US20100226682A1 DEVELOPER CONTAINER, DEVELOPING DEVICE, AND PROCESS CARTRIDGE 失效
标题翻译：开发者集装箱，开发设备和过程盒
公开(公告)号：US20100226682A1
公开(公告)日：2010-09-09
申请号：US12704858
申请日：2010-02-12
申请人： Takayuki Tanaka , Shinichi Nishida , Norio Takahashi , Takahiro Kawamoto
发明人： Takayuki Tanaka , Shinichi Nishida , Norio Takahashi , Takahiro Kawamoto
IPC分类号： G03G15/08 , G03G21/16
CPC分类号： G03G15/0898 , G03G15/0884 , G03G2215/069
摘要： A developer container, which contains a developer to be supplied to a developing chamber in an electrophotographic image forming apparatus, the developer container including: a partition wall partitioning the container from the chamber; a conveying member conveying the developer to an opening in the partition wall to supply the developer to the chamber; a sealing member attached to a wall surface of the partition wall to cover the opening; an extending portion extending from the sealing member to an outside of the container, wherein, when the extending portion is pulled, the sealing member is separated into a remaining portion and a removal portion, and a free end of the remaining portion is positioned below an upper edge of the opening; and a spacing holding member disposed between the wall surface of the partition wall and the sealing member to hold a spacing between the wall surface and the sealing member.
摘要翻译：一种显影剂容器，其包含要供应到电子照相图像形成装置中的显影室的显影剂，所述显影剂容器包括：将容器与所述室分隔开的分隔壁; 将显影剂输送到分隔壁中的开口以将显影剂供应到室的输送构件; 密封构件，其附接到所述分隔壁的壁表面以覆盖所述开口; 从所述密封构件延伸到所述容器的外部的延伸部，其中，当所述延伸部被拉动时，所述密封构件被分离成剩余部分和移除部分，并且所述剩余部分的自由端位于开口的上边缘; 以及间隔保持构件，其设置在所述分隔壁的壁面与所述密封构件之间，以在所述壁表面和所述密封构件之间保持间隔。

39. 发明申请

US20100214054A1 THERMISTOR DEVICE 有权
标题翻译：热敏器件
公开(公告)号：US20100214054A1
公开(公告)日：2010-08-26
申请号：US12706402
申请日：2010-02-16
申请人： Hirokazu Kobayashi , Takayuki Tanaka
发明人： Hirokazu Kobayashi , Takayuki Tanaka
IPC分类号： H01C7/00
CPC分类号： H01C7/18 , G01K7/22 , G01K2205/04 , H01C1/028 , H01C1/148 , H01C7/008
摘要： The present invention relates to a laminate thermistor device comprising a lead terminal 12 connected to a terminal electrode 10. A device main body 4 is a rectangular parallelepiped having mutually perpendicular first side 4a, second side 4b and third side 4c, and when a length of the first side is α, a length of the second side is β and a length of the third side is γ, the length of each side α, β and γ satisfies a relation of α≧β>γ. The terminal electrodes 10 are respectively formed on two plane surfaces including the first side 4a and second side 4b, and the lead terminals 12 are connected to the terminal electrodes 10 respectively to sandwich the third side 4c of the device main body 4 in a length direction therebetween.
摘要翻译：本发明涉及一种层叠热敏电阻器件，其包括连接到端子电极10的引线端子12.器件主体4是具有相互垂直的第一侧4a，第二侧4b和第三侧4c的长方体，并且当长度为第一面是α，第二面的长度为＆bgr; 并且第三侧的长度为γ，每边的长度α＆amp; bgr; γ满足α≧＆Bgr>γ的关系。端子电极10分别形成在包括第一侧面4a和第二侧面4b的两个平面上，并且引线端子12分别连接到端子电极10以将器件主体4的第三侧面4c沿长度方向之间。

40. 发明申请

US20100181680A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD OF THE SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件的半导体器件和制造方法
公开(公告)号：US20100181680A1
公开(公告)日：2010-07-22
申请号：US12688029
申请日：2010-01-15
申请人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Takuya Nakamura
发明人： Yoshimichi Harada , Makoto Murai , Takayuki Tanaka , Takuya Nakamura
IPC分类号： H01L23/16 , H01L21/56 , H01L23/488
CPC分类号： H01L21/563 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16225 , H01L2224/32225 , H01L2224/73203 , H01L2224/73204 , H01L2924/00014 , H01L2924/01012 , H01L2924/01019 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A semiconductor device includes: a mounted body in which a wiring pattern is formed on a first main surface; a semiconductor chip mounted on the surface of the mounted body on which the wiring pattern is formed; an underfill material which is filled between the mounted body and the semiconductor chip and forms a fillet on an outer peripheral part of the semiconductor chip; and an injection section which is disposed on the mounted body and on an outside of a side section, on which the fillet is formed to be longest, of four side sections defining a chip mount area on which the semiconductor chip is mounted, and guides the underfill material to between the mounted body and the semiconductor chip.
摘要翻译：半导体器件包括：安装体，其中在第一主表面上形成布线图案; 安装在其上形成有布线图案的安装体的表面上的半导体芯片; 填充在所述安装体和所述半导体芯片之间的底部填充材料，在所述半导体芯片的外周部形成圆角; 以及喷射部，其设置在所述安装体上并且在所述圆角形状最远的侧部的外侧上限定安装所述半导体芯片的芯片安装区域的四个侧部，并且引导所述注射部底部填充材料到安装体和半导体芯片之间。

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