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31. 发明申请

US20110284865A1 HETEROJUNCTION FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING HETEROJUNCTION FIELD EFFECT TRANSISTOR, AND ELECTRONIC DEVICE 有权
标题翻译：异相场效应晶体管，用于产生异相场效应晶体管的方法和电子器件
公开(公告)号：US20110284865A1
公开(公告)日：2011-11-24
申请号：US13141449
申请日：2009-12-25
申请人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
发明人： Takashi Inoue , Hironobu Miyamoto , Kazuki Ota , Tatsuo Nakayama , Yasuhiro Okamoto , Yuji Ando
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/7787 , H01L29/0843 , H01L29/2003 , H01L29/41766 , H01L29/42316 , H01L29/66462
摘要： A heterojunction filed effect transistor with a low access resistance, a low on resistance, and the like, a method for producing a heterojunction filed effect transistor and an electron device are provided. In the heterojunction field effect transistor, an electron transit layer 11 formed of a III-nitride semiconductor is formed on a substrate 10, an electron supply layer 12 formed of a III-nitride semiconductor forms a heterojunction with an upper surface of the electron transit layer 11, a gate electrode 14, a source electrode 15A, and a drain electrode 15B are arranged on the electron supply layer 12, n-type conductive layer regions 13A and 13B each extended from an upper part of the electron transit layer 11 to an upper surface of the electron supply layer 12 are provided in at least a part below the source electrode 15A and a part below the drain electrode 15B, and an n-type impurity concentration at a heterojunction interface of an electron transit layer 11 part of each of the n-type conductive layer regions 13A and 13B with the electron supply layer 12 is 1×1020 cm−3 or more.
摘要翻译：提供具有低访问阻抗，低导通电阻等的异质结场效应晶体管，提供了异质结场效应晶体管和电子器件的制造方法。在异质结场效应晶体管中，在衬底10上形成由III族氮化物半导体形成的电子迁移层11，由III族氮化物半导体形成的电子供给层12与电子迁移层的上表面形成异质结如图11所示，在电子供给层12上配置有栅电极14，源电极15A和漏电极15B，从电子渡越层11的上部延伸到上部的n型导电层区域13A，13B 电子供给层12的表面设置在源电极15A的下方以及漏电极15B的下方的至少一部分以及电子迁移层11的异质界面的n型杂质浓度具有电子供给层12的n型导电层区域13A，13B为1×1020cm-3以上。

32. 发明申请

US20140084300A1 SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件
公开(公告)号：US20140084300A1
公开(公告)日：2014-03-27
申请号：US14117763
申请日：2012-05-15
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/778 , H01L29/20
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
摘要翻译：场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上，位于源电极和漏电极之间的区域。

33. 发明授权

US08921894B2 Field effect transistor, method for producing the same, and electronic device 有权
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US08921894B2
公开(公告)日：2014-12-30
申请号：US13637555
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/778 , H01L21/8252 , H01L29/78 , H01L29/20 , H01L29/423 , H01L29/66
CPC分类号： H01L29/78 , H01L21/8252 , H01L29/2003 , H01L29/4232 , H01L29/66477 , H01L29/7785 , H01L29/7787
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族原子平面垂直于（0001）晶轴。栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

34. 发明申请

US20130099245A1 FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE 审中-公开
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US20130099245A1
公开(公告)日：2013-04-25
申请号：US13637316
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/205 , H01L29/66 , H01L29/78
CPC分类号： H01L29/205 , H01L29/2003 , H01L29/4232 , H01L29/66431 , H01L29/7785 , H01L29/7787 , H01L29/78
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the lattice-relaxed channel layer 113, and the barrier layer 114 having a tensile strain, and the spacer layer 115 are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面为III族原子平面垂直于（0001）晶轴。晶格弛豫缓冲层112，晶格松弛沟道层113和具有拉伸应变的势垒层114和间隔层115依次层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

35. 发明授权

US08928038B2 Field effect transistor containing a group III nitride semiconductor as main component 有权
标题翻译：含有III族氮化物半导体作为主要成分的场效应晶体管
公开(公告)号：US08928038B2
公开(公告)日：2015-01-06
申请号：US14117763
申请日：2012-05-15
申请人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
发明人： Yasuhiro Okamoto , Yuji Ando , Tatsuo Nakayama , Takashi Inoue , Kazuki Ota
IPC分类号： H01L29/66 , H01L29/778 , H01L29/205 , H01L29/20 , H01L29/423 , H01L29/51
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/201 , H01L29/205 , H01L29/4236 , H01L29/517 , H01L29/66462 , H01L29/7783 , H01L29/7786
摘要： A field effect transistor includes a substrate and a semiconductor layer provided on the substrate, wherein the semiconductor layer includes a lower barrier layer provided on the substrate, Ga-face grown, lattice relaxed, and having a composition In1-zAlzN (0≦z≦1), a channel layer having a composition of: AlxGa1-xN (0≦x≦1) or InyGa1-yN (0≦y≦1). Or GaN provided on and lattice-matched to the lower barrier layer, a source electrode and a drain electrode having ohmic contact to an upper part of the semiconductor layers, disposed spaced to each other, and a gate electrode arranged via a gate insulating film in a region lying between the source electrode and the drain electrode.
摘要翻译：场效应晶体管包括衬底和设置在衬底上的半导体层，其中半导体层包括设置在衬底上的下阻挡层，生长Ga面，晶格弛豫并具有组成In 1-z Al z N（0＆nl; z＆nl E; 1），具有以下组成的沟道层：Al x Ga 1-x N（0＆amp; nlE; x＆nlE; 1）或In y Ga 1-y N（0＆nlE; y＆nlE; 1）。或提供在栅极绝缘膜上并与栅极绝缘膜配置的栅电极，栅极配置在栅极绝缘膜上，栅电极配置在栅极绝缘膜上，位于源电极和漏电极之间的区域。

36. 发明申请

US20130105811A1 FIELD EFFECT TRANSISTOR, METHOD FOR PRODUCING THE SAME, AND ELECTRONIC DEVICE 有权
标题翻译：场效应晶体管，其制造方法和电子器件
公开(公告)号：US20130105811A1
公开(公告)日：2013-05-02
申请号：US13637555
申请日：2010-12-15
申请人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
发明人： Yuji Ando , Takashi Inoue , Kazuki Ota , Yasuhiro Okamoto , Tatsuo Nakayama , Kazuomi Endo
IPC分类号： H01L29/78 , H01L29/66 , H01L29/20
CPC分类号： H01L29/78 , H01L21/8252 , H01L29/2003 , H01L29/4232 , H01L29/66477 , H01L29/7785 , H01L29/7787
摘要： The present invention provides a field effect transistor which can achieve both of a high threshold voltage and a low on-state resistance, a method for producing the same, and an electronic device. In the field effect transistor, each of a buffer layer 112, a channel layer 113, a barrier layer 114, and a spacer layer 115 is formed of a group-III nitride semiconductor, and each of the upper surfaces thereof is a group-III atomic plane that is perpendicular to a (0001) crystal axis. The lattice-relaxed buffer layer 112, the channel layer 113 having a compressive strain, and the barrier layer 114 having a tensile strain, and the spacer layer 115 having a compressive strain are laminated on a substrate 100 in this order. The gate insulating film 14 is arranged on the spacer layer 115. The gate electrode 15 is arranged on the gate insulating film 14. The source electrode 161 and the drain electrode 162 are electrically connected to the channel layer 113 directly or via another component.
摘要翻译：本发明提供了能够实现高阈值电压和低通态电阻两者的场效应晶体管，其制造方法和电子器件。在场效应晶体管中，由III族氮化物半导体形成缓冲层112，沟道层113，势垒层114和间隔层115，其上表面分别为III族原子平面垂直于（0001）晶轴。栅格弛豫缓冲层112，具有压缩应变的沟道层113和具有拉伸应变的阻挡层114以及具有压缩应变的间隔层115以此顺序层压在基板100上。栅极绝缘膜14布置在间隔层115上。栅电极15布置在栅极绝缘膜14上。源极161和漏极162直接或经由另一个部件电连接到沟道层113。

37. 发明申请

US20100155779A1 Field Effect Transistor 审中-公开
标题翻译：场效应晶体管
公开(公告)号：US20100155779A1
公开(公告)日：2010-06-24
申请号：US11992755
申请日：2006-09-28
申请人： Yasuhiro Murase , Kazuki Ota , Yasuhiro Okamoto , Kouji Matsunaga , Hironobu Miyamoto
发明人： Yasuhiro Murase , Kazuki Ota , Yasuhiro Okamoto , Kouji Matsunaga , Hironobu Miyamoto
IPC分类号： H01L29/78
CPC分类号： H01L29/7787 , H01L29/2003 , H01L29/405 , H01L29/66462
摘要： In a field effect transistor, a Group III nitride semiconductor layer structure containing a hetero junction, a source electrode 101 and a drain electrode 103 formed apart from each other over the Group III nitride semiconductor layer structure, and a gate electrode 102 disposed between these electrodes, are provided. Over the surface of the Group III nitride semiconductor layer structure, a SiO2 film 122 containing oxygen as a constitutive element is provided, in contact with both side faces of the gate electrode 102. Over the surface of the Group III nitride semiconductor layer structure, a SiN film 121 is provided so as to cover the region between the SiO2 film 122 and the source electrode 101, and the region between the SiO2 film 122 and the drain electrode 103. The SiN film 121 is composed of a material different from that composing the SiO2 film 122, and contains nitrogen as a constitutive element.
摘要翻译：在场效应晶体管中，包含异质结的III族氮化物半导体层结构，在III族氮化物半导体层结构上彼此分开形成的源电极101和漏极103以及设置在这些电极之间的栅极102 ，提供。在III族氮化物半导体层结构的表面上，提供含有氧作为构成元素的SiO 2膜122，与栅电极102的两个侧面接触。在III族氮化物半导体层结构的表面上， SiN膜121被设置为覆盖SiO 2膜122和源电极101之间的区域以及SiO 2膜122和漏电极103之间的区域。SiN膜121由与不同于构成 SiO 2膜122，并且含有氮作为构成元素。

38. 发明申请

US20110291160A1 FIELD EFFECT TRANSISTOR 有权
标题翻译：场效应晶体管
公开(公告)号：US20110291160A1
公开(公告)日：2011-12-01
申请号：US13147676
申请日：2010-02-03
申请人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
发明人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
IPC分类号： H01L29/778
CPC分类号： H01L29/4236 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/66621 , H01L29/7783 , H01L29/7787
摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0
摘要翻译：场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112），其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0＆lt; n 1; 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105）其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。氮化物系半导体多层结构中的各层的Al组成满足0

39. 发明授权

US08618578B2 Field effect transistor 有权
标题翻译：场效应晶体管
公开(公告)号：US08618578B2
公开(公告)日：2013-12-31
申请号：US13147676
申请日：2010-02-03
申请人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
发明人： Kazuki Ota , Yasuhiro Okamoto , Hironobu Miyamoto
IPC分类号： H01L29/66
CPC分类号： H01L29/4236 , H01L29/1029 , H01L29/2003 , H01L29/42316 , H01L29/66462 , H01L29/66621 , H01L29/7783 , H01L29/7787
摘要： A field effect transistor includes a nitride-based semiconductor multi-layer structure, a source electrode (108), a drain electrode (109), a protective film (110), and a gate electrode (112) that is provided in a recess structure, which is formed by etching, directly or with a gate insulating film interposed therebetween. The nitride-based semiconductor multi-layer structure includes at least a base layer (103) made of AlXGa1-XN (0≦1), a channel layer (104) made of GaN or InGaN, a first electron supply layer (105), which is an undoped or n-type AlYGa1-YN layer, a threshold value control layer (106), which is an undoped AlZGa1-ZN layer, and a second electron supply layer (107), which is an undoped or n-type AlWGa1-WN layer, epitaxially grown in this order on a substrate (101) with a buffer layer (102) interposed therebetween. The Al composition of each layer in the nitride-based semiconductor multi-layer structure satisfies 0
摘要翻译：场效应晶体管包括氮化物基半导体多层结构，源电极（108），漏电极（109），保护膜（110）和设置在凹槽结构中的栅电极（112），其通过蚀刻直接形成，或者在其间插入栅极绝缘膜。所述氮化物系半导体多层结构至少包括由Al x Ga 1-x N（0 1）构成的基极层（103），由GaN或InGaN构成的沟道层（104），第1电子供给层（105）其是未掺杂的或n型AlYGa1-YN层，作为未掺杂的AlZGa1-ZN层的阈值控制层（106）和作为未掺杂的或n型AlWGa1的第二电子供给层（107） -WN层，在衬底（101）上依次外延生长，缓冲层（102）插入其间。氮化物类半导体多层结构中的各层的Al组成满足0

40. 发明授权

US06534790B2 Compound semiconductor field effect transistor 有权
标题翻译：复合半导体场效应晶体管
公开(公告)号：US06534790B2
公开(公告)日：2003-03-18
申请号：US09796803
申请日：2001-03-02
申请人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
发明人： Takehiko Kato , Kazuki Ota , Hironobu Miyamoto , Naotaka Iwata , Masaaki Kuzuhara
IPC分类号： H01L2915
CPC分类号： H01L29/66462 , H01L29/7785
摘要： The present invention provides a field effect transistor (FET) having, on a semi-insulating compound semiconductor substrate, a buffer layer; an active layer that includes a channel layer made of a first conductive-type epitaxial growth layer (e.g. InGaAs); source/drain electrodes formed on a first conductive-type contact layer which is formed either on said active layer or on a lateral face thereof; a gate layer made of a second conductive-type epitaxial growth layer (e.g. p+-GaAs); and a gate electrode formed on said gate layer; which further has, between said second conductive-type gate layer and said channel layer, a semiconductor layer (e.g. InGaP) that rapidly lowers the energy of the valance band spreading from said gate layer to said channel layer. The present invention improves withstand voltage characteristic of a FET having a pn junction in a gate region (JFET) and realizes stable operations of a JFET.
摘要翻译：本发明提供一种在半绝缘化合物半导体衬底上具有缓冲层的场效应晶体管（FET）包括由第一导电型外延生长层（例如InGaAs）制成的沟道层的有源层; 源极/漏极，形成在形成在所述有源层上或其侧面上的第一导电型接触层上; 由第二导电型外延生长层（例如p + -GaAs）制成的栅极层; 以及形成在所述栅极层上的栅电极; 在所述第二导电型栅极层和所述沟道层之间还具有快速降低从所述栅极层扩散到所述沟道层的能带的能量的半导体层（例如InGaP）。本发明提高了在栅极区（JFET）中具有pn结的FET的耐压特性，并且实现了JFET的稳定操作。

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