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31. 发明授权

US5596520A CMOS full adder circuit with pair of carry signal lines 失效
标题翻译： CMOS全加器电路与一对进位信号线
公开(公告)号：US5596520A
公开(公告)日：1997-01-21
申请号：US317435
申请日：1994-10-04
申请人： Hiroyuki Hara , Takayasu Sakurai
发明人： Hiroyuki Hara , Takayasu Sakurai
IPC分类号： G06F7/50 , G06F7/503 , G06F7/506
CPC分类号： G06F7/503 , G06F2207/3872
摘要： A full adder circuit has a plurality of full adders each provided for each bit. Each full adder has: a calculation block (31a) responsive to a first carry signal (C) given by a preceding stage bit as a differential signal and two external input data (A1, B1) to be added at a present stage bit, for outputting addition data calculated on the basis of the first carry signal and the external input data as two differential signals, and further outputting a second carry signal (/C) to a succeeding bit as a differential signal indicative of whether a carry is generated by the present stage bit or not. Each full adder also has a latch type sense amplifier (16a) for outputting an addition result (SUM) of the present stage bit, after having differentially amplified and latched the addition data outputted by the calculation block. Since the addition operation is made on the basis of the carry signals (C and /C) of a minute potential difference (before amplification), it is possible to shorten the required charging time and to reduce the current consumption. In addition, since the sense amplifiers (16a) are provided with the latch function (18a), it is possible to control the differential amplification operation and the latch operation on the basis of a common sense amplifier activating signal (SAB), so that the number of elements can be reduced.
摘要翻译：全加器电路具有各自为每个位提供的多个全加器。每个全加器具有：响应于由前级位给出的第一进位信号（C）作为差分信号的计算块（31a）和要在当前级位相加的两个外部输入数据（A1，B1），用于输出基于第一进位信号和外部输入数据计算的加法数据作为两个差分信号，并且还将第二进位信号（/ C）输出到后一位，作为指示是否由现在阶段位或不。每个全加器还具有锁存型读出放大器（16a），用于在差分放大并锁存由计算块输出的相加数据之后输出当前级位的相加结果（SUM）。由于根据微小电位差（放大之前）的进位信号（C和/ C）进行加法运算，因此可以缩短所需的充电时间并降低电流消耗。此外，由于读出放大器（16a）具有锁存功能（18a），所以可以根据公共放大器激活信号（SAB）来控制差分放大操作和锁存器操作，使得元素数量可以减少。

32. 发明授权

US5459342A Field programmable gate array with spare circuit block 失效
标题翻译：具有备用电路块的现场可编程门阵列
公开(公告)号：US5459342A
公开(公告)日：1995-10-17
申请号：US146312
申请日：1993-11-02
申请人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
发明人： Kazutaka Nogami , Takayasu Sakurai , Fumitoshi Hatori
IPC分类号： H01L21/82 , G06F11/20 , H01L27/118 , H03K19/173 , H01L21/70 , H01L27/00 , H03K19/177
CPC分类号： H03K19/17764
摘要： A field programmable gate array, comprises: a plurality of circuit blocks each having logic circuits; at least one spare circuit block having logic circuits; a set of interconnections including at least one interconnection for connecting at least one of the circuit blocks and the at least one spare circuit programmably; and at least one connecting element disposed on the interconnection of the set of interconnections which turns its status from a turned-on state to a turned-off state or vice versa when programmed. When any one of the circuit blocks is defective, since the defective circuit block can be replaced with the spare circuit block, it is possible to retain any desired functions of the logic circuits by programming the connecting means, thus improving the production yield of the field programmable gate array and thereby reducing the manufacturing cost thereof.
摘要翻译：现场可编程门阵列包括：多个具有逻辑电路的电路块; 至少一个具有逻辑电路的备用电路块; 一组互连，其包括至少一个互连，用于可编程地连接至少一个所述电路块和所述至少一个备用电路; 以及至少一个连接元件，其设置在所述一组互连件的互连上，其在编程时将其状态从打开状态转变为关闭状态，反之亦然。当任何一个电路块有缺陷时，由于可以用备用电路块代替有缺陷的电路块，可以通过编程连接装置来保持逻辑电路的所需功能，从而提高了现场的产量可编程门阵列，从而降低其制造成本。

33. 发明授权

US5294911A Data comparator 失效
标题翻译：数据比较器
公开(公告)号：US5294911A
公开(公告)日：1994-03-15
申请号：US841638
申请日：1992-02-27
申请人： Masanori Uchida , Takayasu Sakurai
发明人： Masanori Uchida , Takayasu Sakurai
IPC分类号： G06F7/04 , G06F7/02 , G06F12/10 , G11C15/04 , H03K19/0175 , H03K19/08 , G05B1/03
CPC分类号： G06F7/02
摘要： According to this invention, a bit data comparing section has a plurality of groups each having a plurality of bit comparators. Each of the plurality of bit comparators compares one bit of address data input to the bit comparator with bit data stored in the bit comparator in advance and outputs a comparison result. Output data from a plurality of bit comparators belonging to one group are unified by one subsense line belonging to the group and input to a control terminal of a switching element. The switching element performs a switching operation in accordance with the input data. A main sense line is connected to the switching element, and a load circuit is connected between the main sense line and a power supply terminal.
摘要翻译：根据本发明，位数据比较部分具有多个组，每组具有多个位比较器。多个位比较器中的每一个比较器预先将输入到位比较器的地址数据的一位与存储在位比较器中的位数据进行比较，并输出比较结果。属于一组的多个位比较器的输出数据由属于该组的一个子线统一，并输入到开关元件的控制端。开关元件根据输入数据执行切换操作。主感测线连接到开关元件，并且负载电路连接在主感测线和电源端子之间。

34. 发明授权

US4974203A Arrangement and construction of an output control circuit in a semiconductor memory device 失效
标题翻译：半导体存储器件中输出控制电路的布置和结构
公开(公告)号：US4974203A
公开(公告)日：1990-11-27
申请号：US274594
申请日：1988-11-22
申请人： Takayasu Sakurai
发明人： Takayasu Sakurai
IPC分类号： G11C11/409 , G11C7/10 , G11C11/401
CPC分类号： G11C7/1048
摘要： A semiconductor memory device includes output control circuits which are located adjacent to column sense amplifiers and output transistors which are located at a distance from the output control circuits. The wiring length of a first wiring from the column sense amplifiers to the output control circuits is set to be shorter than the wiring length of a second wiring from the output control circuits to the output transistors. The second wiring has a parasitic capacitance at least five times the parasitic capacitance of the first wiring.

35. 发明授权

US4866677A Semiconductor memory device with multiple alternating decoders coupled to each word line 失效
标题翻译：具有耦合到每个字线的多个交替解码器的半导体存储器件
公开(公告)号：US4866677A
公开(公告)日：1989-09-12
申请号：US208786
申请日：1988-06-17
申请人： Takayasu Sakurai
发明人： Takayasu Sakurai
IPC分类号： G11C11/407 , G11C11/403 , G11C11/406 , G11C11/408 , G11C11/413 , H01L29/94
CPC分类号： G11C11/406
摘要： A semiconductor memory device includes a first row decoder and memory cells M11 to MNL. The first row decoder receives the row address signal from an input buffer and a specific row fo a matrix array of memory cells M11 to MNL. The memory device further includes a second row decoder, a refresh address generator, a timing controller and switching circuits. The second row decoder selects a specific row of the matrix array according to a refresh address derived from the refresh address generator. The output terminals of the first and second row decoders, are connected to the memory cells through groups of switching circuits. The timing controller selectively renders conductive either the switching circuit group.
摘要翻译：半导体存储器件包括第一行解码器和存储单元M11至MNL。第一行解码器从存储单元M11至MNL的矩阵阵列的输入缓冲器和特定行接收行地址信号。存储器件还包括第二行解码器，刷新地址发生器，定时控制器和开关电路。第二行解码器根据从刷新地址生成器导出的刷新地址来选择矩阵阵列的特定行。第一行解码器和第二行解码器的输出端子通过开关电路组连接到存储器单元。定时控制器选择性地使开关电路组导通。

36. 发明授权

US4827453A Semiconductor memory control circuit 失效
标题翻译：半导体存储器控制电路
公开(公告)号：US4827453A
公开(公告)日：1989-05-02
申请号：US127261
申请日：1987-12-01
申请人： Kazuhiro Sawada , Takayasu Sakurai
发明人： Kazuhiro Sawada , Takayasu Sakurai
IPC分类号： G11C11/407 , G11C7/22 , G11C8/18 , G11C11/403 , G11C11/406 , G11C11/4076 , G11C7/00
CPC分类号： G11C7/22 , G11C11/406 , G11C11/4076 , G11C8/18
摘要： A semiconductor memory control circuit separates an externally input operation activation signal from an operation activation signal which is transferred inside a memory, and activates the internal operation activation signal only for a predetermined period of time. This predetermined period is determined in accordance with the cycle time required to achieve refreshment of a memory cell after the external operation activation signal is activated. Thereafter, even if the external operation activation signal is in an activated state, the internal operation activation signal is inactivated. When the internal operation activation signal is in the activated state and the external operation activation signal is inactivated, the internal operation activation signal is inactivated, in accordance with activation of the external operation activation signal.

37. 发明授权

US4757217A Refresh operation control circuit for semiconductor device 失效
标题翻译：半导体器件的刷新操作控制电路
公开(公告)号：US4757217A
公开(公告)日：1988-07-12
申请号：US11882
申请日：1987-02-06
申请人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
发明人： Kazuhiro Sawada , Takayasu Sakurai , Kazutaka Nogami
IPC分类号： G11C11/403 , G11C11/406 , H03K3/356
CPC分类号： G11C11/406
摘要： This invention provides a refresh operation control circuit for a semiconductor memory device. Two flip-flop circuits respectively temporarily hold a normal read start command signal and a refresh start command signal generated within the memory device. A normal operation/refresh operation priority determining circuit wherein 2-input logic circuits are cross-connected so that one output in each case of each of these two flip-flop circuits provides one input of the other flip-flop circuit. The priority determining circuit determines the priority of normal read operation and refresh operation in accordance with the logic level relationship of the one inputs. Either control of the start of normal read operation or control of the start of refresh operation is carried out in accordance with the output of this determination.

38. 发明授权

US4744063A Static memory utilizing transition detectors to reduce power consumption 失效
标题翻译：静态存储器利用转换检测器来降低功耗
公开(公告)号：US4744063A
公开(公告)日：1988-05-10
申请号：US613614
申请日：1984-05-24
申请人： Takayuki Ohtani , Takayasu Sakurai , Mitsuo Isobe , Tetsuya Iizuka
发明人： Takayuki Ohtani , Takayasu Sakurai , Mitsuo Isobe , Tetsuya Iizuka
IPC分类号： G11C11/41 , G11C8/18 , G11C11/418 , G11C16/06 , G11C8/00
CPC分类号： G11C11/418 , G11C8/18
摘要： A static memory has an address transition detector, an input data transition detector and a pulse signal generator. When a detector detects that an input address or input data has changed, the pulse signal generator produces a pulse signal having a width longer than the shorter of the data-reading or data-writing cycle. This pulse signal controls the period of time during which a penetrating DC current flows between two power sources via some of the components of the memory.
摘要翻译：静态存储器具有地址转换检测器，输入数据转换检测器和脉冲信号发生器。当检测器检测到输入地址或输入数据已经改变时，脉冲信号发生器产生具有比数据读取或数据写入周期更短的宽度的脉冲信号。该脉冲信号控制穿透DC电流通过存储器的一些部件在两个电源之间流动的时间段。

39. 发明授权

US4677592A Dynamic RAM 失效
标题翻译：动态RAM
公开(公告)号：US4677592A
公开(公告)日：1987-06-30
申请号：US739171
申请日：1985-05-30
申请人： Takayasu Sakurai , Tetsuya Iizuka
发明人： Takayasu Sakurai , Tetsuya Iizuka
IPC分类号： G11C11/403 , G11C11/406 , G11C7/00
CPC分类号： G11C11/40615 , G11C11/406
摘要： In a dynamic RAM, the refreshing operation is performed during one cycle of the read or write operation. A switch circuit selects either a row address signal output from address input circuit or a refresh row address signal output from a refresh circuit. By controlling the switch circuit by a switch selector, the refresh is performed during the operation delay time of the address input circuit or an input/output circuit for inputting and outputting data.
摘要翻译：在动态RAM中，刷新操作在读取或写入操作的一个周期期间执行。开关电路选择从地址输入电路输出的行地址信号或从刷新电路输出的刷新行地址信号。通过开关选择器控制开关电路，在地址输入电路的操作延迟时间或输入和输出数据的输入/输出电路中进行刷新。

40. 发明授权

US4555778A Semiconductor memory device 失效
标题翻译：半导体存储器件
公开(公告)号：US4555778A
公开(公告)日：1985-11-26
申请号：US636220
申请日：1984-07-31
申请人： Takayasu Sakurai
发明人： Takayasu Sakurai
IPC分类号： G11C11/41 , G11C7/10 , G11C8/12 , G11C8/14 , G11C11/413 , G11C8/00
CPC分类号： G11C7/10 , G11C8/12 , G11C8/14
摘要： Disclosed is a semiconductor memory device in which a group of memory cells consists of a plurality of memory sections, each memory section is provided with a first data line, and a second data line is provided for connecting together the first data lines.
摘要翻译：公开了一种半导体存储器件，其中一组存储器单元由多个存储器部分组成，每个存储器部分设置有第一数据线，并且第二数据线被提供用于将第一数据线连接在一起。

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