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    • 32. 发明授权
    • Ultra-high aspect ratio dielectric etch
    • 超高纵横比电介质蚀刻
    • US07682986B2
    • 2010-03-23
    • US11671340
    • 2007-02-05
    • Kyeong-Koo ChiErik A. Edelberg
    • Kyeong-Koo ChiErik A. Edelberg
    • H01L21/302
    • H01L21/31144H01L21/31116H01L21/31138H01L21/76816
    • A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
    • 提供了一种通过碳基掩模蚀刻介电层中的超高宽比特征的方法。 相对于碳基掩模选择性地蚀刻电介质层,其中选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。 选择性蚀刻停止。 相对于碳基掩模选择性地除去氟碳聚合物,使得使用修整保留碳基掩模。 停止选择性除去氟碳聚合物。 相对于碳基掩模再次选择性地蚀刻介电层,其中第二选择性蚀刻提供基于碳基掩模的碳氟基聚合物的净沉积。
    • 35. 发明申请
    • LINE WIDTH ROUGHNESS CONTROL WITH ARC LAYER OPEN
    • 线宽宽度控制与弧层开放
    • US20090087996A1
    • 2009-04-02
    • US12210777
    • 2008-09-15
    • Kyeong-Koo ChiJonathan Kim
    • Kyeong-Koo ChiJonathan Kim
    • H01L21/3065
    • H01L21/31116H01L21/31144
    • To achieve the foregoing and in accordance with the purpose of the present invention a method for etching an etch layer disposed below an antireflective coating (ARC) layer below a patterned mask is provided. The ARC layer is opened, and features are etched into the etch layer through the patterned mask. The opening the ARC layer includes (1) providing an ARC opening gas comprising a halogen containing gas, COS, and an oxygen containing gas, (2) forming a plasma from the ARC opening gas to open the ARC layer, and (3) stopping providing the ARC opening gas to stop the plasma. The patterned mask may be a photoresist (PR) mask having a line-space pattern. COS in the ARC opening gas reduces line width roughness (LWR) of the patterned features of the etch layer.
    • 为了实现上述目的,并且根据本发明的目的,提供了一种用于蚀刻设置在图案化掩模下面的抗反射涂层(ARC)层下方的蚀刻层的方法。 ARC层被打开,并且通过图案化掩模将特征蚀刻到蚀刻层中。 ARC层的开口包括(1)提供包含含卤素气体COS和含氧气体的ARC开口气体,(2)从ARC开口气体形成等离子体以打开ARC层,以及(3)停止 提供ARC打开的气体来停止等离子体。 图案化掩模可以是具有线间隔图案的光致抗蚀剂(PR)掩模。 ARC打开气体中的COS降低蚀刻层的图案化特征的线宽粗糙度(LWR)。
    • 37. 发明授权
    • DRAM cell
    • DRAM单元
    • US06855597B2
    • 2005-02-15
    • US10413372
    • 2003-04-15
    • Chul-Ho ShinKyeong-Koo Chi
    • Chul-Ho ShinKyeong-Koo Chi
    • H01L21/02H01L21/8242H01L27/108
    • H01L27/10855H01L27/10885H01L28/91
    • A method of manufacturing a DRAM cell includes forming an isolation layer on a given region of a substrate to define an active region having a plurality of line shaped sub-regions; forming at least a pair of cell transistors in each line shaped sub-region, each cell transistor of a pair having a common drain region and respective source regions; forming a bit line pad on each common drain region and a storage node pad on each source region; forming a bit line pad protecting layer pattern having portions parallel to the word line, that covers the bit line pad; and forming storage nodes on storage node pads. The storage nodes of the DRAM cell contact with the storage node pads and are insulated electrically from the bit line pad by the bit pad protecting layer pattern.
    • 制造DRAM单元的方法包括在衬底的给定区域上形成隔离层以限定具有多个线状子区域的有源区域; 在每个线状子区域中形成至少一对单元晶体管,每对单元晶体管具有公共漏极区域和相应的源极区域; 在每个公共漏极区域上形成位线焊盘和在每个源极区域上形成存储节点焊盘; 形成具有与字线平行的部分的位线保护层图案,覆盖位线焊盘; 并在存储节点垫上形成存储节点。 DRAM单元的存储节点与存储节点焊盘接触,并通过位焊盘保护层图案与位线焊盘电绝缘。
    • 39. 发明授权
    • Methods of fabricating nonvolatile memory devices
    • 制造非易失性存储器件的方法
    • US07510934B2
    • 2009-03-31
    • US11807544
    • 2007-05-29
    • Seung-Pil ChungJong-Ho ParkKyeong-Koo ChiDong-Hyun Kim
    • Seung-Pil ChungJong-Ho ParkKyeong-Koo ChiDong-Hyun Kim
    • H01L21/336
    • H01L27/11521H01L27/115
    • A nonvolatile memory device includes a semiconductor substrate, a device isolation film, a tunnel insulation film, a plurality of floating gates, an inter-gate dielectric film, and a control gate pattern. Trenches are formed in the substrate that define active regions therebetween. The device isolation film is in the trenches in the substrate. The tunnel insulation film is on the active regions of the substrate. The plurality of floating gates are each on the tunnel insulation film over the active regions of the substrate. The inter-gate dielectric film extends across the floating gates and the device isolation film. The control gate pattern is on the inter-gate dielectric film and extends across the floating gates. A central region of the device isolation film in the trenches has an upper major surface that is recessed below an upper major surface of a surrounding region of the device isolation film in the trenches. An edge of the recessed central region of the device isolation film is aligned with a sidewall of an adjacent one of the floating gates.
    • 非易失性存储器件包括半导体衬底,器件隔离膜,隧道绝缘膜,多个浮置栅极,栅极间电介质膜和控制栅极图案。 沟槽形成在衬底中,其间限定有效区域。 器件隔离膜位于衬底中的沟槽中。 隧道绝缘膜位于衬底的有源区上。 多个浮置栅极分别位于衬底的有源区上的隧道绝缘膜上。 栅极间电介质膜延伸穿过浮栅和器件隔离膜。 控制栅极图案在栅极间电介质膜上并且跨越浮动栅极延伸。 沟槽中的器件隔离膜的中心区域具有在沟槽中的器件隔离膜的周围区域的上主表面下方凹陷的上主表面。 器件隔离膜的凹入的中心区域的边缘与相邻的一个浮动栅极的侧壁对准。
    • 40. 发明申请
    • ULTRA-HIGH ASPECT RATIO DIELECTRIC ETCH
    • 超高比例电介质蚀刻
    • US20080188081A1
    • 2008-08-07
    • US11671340
    • 2007-02-05
    • Kyeong-Koo ChiErik A. Edelberg
    • Kyeong-Koo ChiErik A. Edelberg
    • H01L21/311H01L21/461
    • H01L21/31144H01L21/31116H01L21/31138H01L21/76816
    • A method for etching an ultra high aspect ratio feature in a dielectric layer through a carbon based mask is provided. The dielectric layer is selectively etched with respect to the carbon based mask, wherein the selective etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask. The selective etch is stopped. The fluorocarbon polymer is selectively removed with respect to the carbon based mask, so that the carbon based mask remains, using a trimming. The selectively removing the fluorocarbon polymer is stopped. The dielectric layer is again selectively etched with respect to the carbon based mask, wherein the second selectively etching provides a net deposition of a fluorocarbon based polymer on the carbon based mask.
    • 提供了一种通过碳基掩模蚀刻介电层中的超高宽比特征的方法。 相对于碳基掩模选择性地蚀刻电介质层,其中选择性蚀刻提供基于碳基掩模的基于碳氟化合物的聚合物的净沉积。 选择性蚀刻停止。 相对于碳基掩模选择性地除去氟碳聚合物,使得使用修整保留碳基掩模。 停止选择性除去氟碳聚合物。 相对于碳基掩模再次选择性地蚀刻介电层,其中第二选择性蚀刻提供基于碳基掩模的碳氟基聚合物的净沉积。