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31. 发明授权

US06518642B2 Integrated circuit having a passive device integrally formed therein 有权
公开(公告)号：US06518642B2
公开(公告)日：2003-02-11
申请号：US09878118
申请日：2001-06-06
申请人： Hong-Soo Kim , Joon-Hee Lee
发明人： Hong-Soo Kim , Joon-Hee Lee
IPC分类号： H01L2900
CPC分类号： H01L21/76802 , H01L21/3185 , H01L21/76838 , H01L23/5258 , H01L27/0629 , H01L28/10 , H01L28/20 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： The invented method and device provide a reliable contact to a passive device of a semiconductor circuit device, the passive device being, for example, a resistor, an inductor, a fuse or the like. Adjacent, spaced, elevated, so-called dummy pattern (shoulder) regions are formed under the portions of the passive device on which the contact hole is formed. The shoulder region is formed of the same material as the first conductive layer of the gate of the peripheral transistor. The electrode may be formed through the contact hole to be a reliable contact to the integrated passive device.

32. 发明授权

US08986833B2 Enamel varnish composition for enamel wire and enamel wire using same 有权
标题翻译：搪瓷线漆和搪瓷线漆用漆组合物
公开(公告)号：US08986833B2
公开(公告)日：2015-03-24
申请号：US11816780
申请日：2005-05-27
申请人： Joon-Hee Lee
发明人： Joon-Hee Lee
IPC分类号： B32B15/00 , C08G73/14 , C08F126/06 , C09J179/08 , H01B3/30
CPC分类号： C09J179/08 , C08G73/14 , H01B3/305 , H01B3/306 , Y10T428/2933 , Y10T428/2947
摘要： Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost layer, has the increased adhesivity of the insulated coating layer to the conducting wire, as well as the excellent physical properties such as the wear resistance and flexibility, etc.
摘要翻译：公开了用于搪瓷丝的搪瓷清漆组合物和使用其的搪瓷丝。本发明涉及一种搪瓷丝的搪瓷清漆组合物，其中聚合物树脂组分包含在有机溶剂中，其中聚合物树脂组分包括第一聚酰胺酰亚胺树脂; 和具有聚酰胺酰亚胺的第二树脂，其中三嗪环被引入主链。将这种涂料颜料组合物施加到最内层的搪瓷丝具有增加的绝缘涂层对导线的粘合性以及优异的物理性能如耐磨性和柔性等。

33. 发明授权

US08372711B2 Methods of fabricating semiconductor devices with sidewall conductive patterns 有权
标题翻译：制造具有侧壁导电图案的半导体器件的方法
公开(公告)号：US08372711B2
公开(公告)日：2013-02-12
申请号：US13110113
申请日：2011-05-18
申请人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
发明人： Jong-Sun Sel , Jung-Dal Choi , Joon-Hee Lee , Hwa-Kyung Shin
IPC分类号： H01L21/336
CPC分类号： H01L27/11526 , H01L21/28273 , H01L27/105 , H01L27/11529
摘要： A gate pattern is disclosed that includes a semiconductor substrate, a lower conductive pattern, an upper conductive pattern, and a sidewall conductive pattern. The lower conductive pattern is on the substrate. The insulating pattern is on the lower conductive pattern. The upper conductive pattern is on the insulating pattern opposite to the lower conductive pattern. The sidewall conductive pattern is on at least a portion of sidewalls of the upper conductive pattern and the lower conductive pattern. The sidewall conductive pattern electrically connects the upper conductive pattern and the lower conductive pattern. An upper edge portion of the lower conductive pattern may be recessed relative to a lower edge portion of the lower conductive pattern to define a ledge thereon. The sidewall conductive pattern may be directly on the ledge and sidewall of the recessed upper edge portion of the lower conductive pattern.
摘要翻译：公开了一种栅极图案，其包括半导体衬底，下导电图案，上导电图案和侧壁导电图案。下导电图案在基板上。绝缘图案位于下导电图案上。上导电图案位于与下导电图案相对的绝缘图案上。侧壁导电图案位于上导电图案和下导电图案的侧壁的至少一部分上。侧壁导电图形电连接上导电图案和下导电图案。下导电图案的上边缘部分可以相对于下导电图案的下边缘部分凹进，以在其上限定凸缘。侧壁导电图案可以直接在下导电图案的凹陷的上边缘部分的凸缘和侧壁上。

34. 发明申请

US20130032871A1 SEMICONDUCTOR DEVICE HAVING AIR GAP AND METHOD OF FABRICATING THE SAME 有权
标题翻译：具有空气隙的半导体器件及其制造方法
公开(公告)号：US20130032871A1
公开(公告)日：2013-02-07
申请号：US13564117
申请日：2012-08-01
申请人： Yoo-Cheol SHIN , Joon-Hee Lee
发明人： Yoo-Cheol SHIN , Joon-Hee Lee
IPC分类号： H01L29/788
CPC分类号： H01L21/764 , H01L27/11521
摘要： A semiconductor device includes tunneling insulating layers on active regions of a substrate, floating gate electrodes on the tunneling insulating layers, an isolation trench within the substrate and the isolation trench defines the active region, spaces the tunneling insulating layers, and isolates the floating gate electrodes. A bottom of the isolation trench is directly in contact with the substrate. The semiconductor device further includes a lower insulating layer on the floating gate electrodes, and a middle insulating layer, an upper insulating layer, and a control gate electrode stacked on the lower insulating layer. The lower insulating layer is configured to hermetically seal a top portion of the isolation trench to define and directly abut an air gap within the isolation trench.
摘要翻译：半导体器件包括在衬底的有源区上的隧道绝缘层，隧道绝缘层上的浮动栅电极，衬底内的隔离沟槽，隔离沟槽限定有源区，使隧道绝缘层隔开，并隔离浮置栅电极。隔离沟槽的底部直接与衬底接触。半导体器件还包括浮置栅电极上的下绝缘层，以及堆叠在下绝缘层上的中间绝缘层，上绝缘层和控制栅电极。下绝缘层被配置为气密地密封隔离沟槽的顶部以限定和直接邻接隔离沟槽内的气隙。

35. 发明申请

US20090202830A1 ENAMEL VARNISH COMPOSITION FOR ENAMEL WIRE AND ENAMEL WIRE USING SAME 有权
标题翻译： ENAMEL VARNISH组合物用于ENAMEL线和ENAMEL线使用相同
公开(公告)号：US20090202830A1
公开(公告)日：2009-08-13
申请号：US11816780
申请日：2005-05-27
申请人： Joon-Hee Lee
发明人： Joon-Hee Lee
IPC分类号： B32B15/08 , B32B15/02 , C08L33/24
CPC分类号： C09J179/08 , C08G73/14 , H01B3/305 , H01B3/306 , Y10T428/2933 , Y10T428/2947
摘要： Disclosed are enamel varnish compositions for an enamel wire and an enamel wire using the same. The present invention relates to enamel varnish compositions for an enamel wire in which a polymeric resin component is included in an organic solvent, wherein the polymeric resin component includes a first polyamideimide resin; and a second resin having polyamideimide in which a triazine ring is introduced into a major chain. The enamel wire, in which such a coating pigment composition is applied to the innermost layer, has the increased adhesivity of the insulated coating layer to the conducting wire, as well as the excellent physical properties such as the wear resistance and flexibility, etc.
摘要翻译：公开了用于搪瓷丝的搪瓷清漆组合物和使用其的搪瓷丝。本发明涉及一种搪瓷丝的搪瓷清漆组合物，其中聚合物树脂组分包含在有机溶剂中，其中聚合物树脂组分包括第一聚酰胺酰亚胺树脂; 和具有聚酰胺酰亚胺的第二树脂，其中三嗪环被引入主链。将这种涂料颜料组合物施加到最内层的搪瓷丝具有增加的绝缘涂层对导线的粘合性以及优异的物理性能如耐磨性和柔性等。

36. 发明申请

US20080268218A1 INSULATED ELECTRIC WIRE 审中-公开
标题翻译：绝缘电线
公开(公告)号：US20080268218A1
公开(公告)日：2008-10-30
申请号：US11942115
申请日：2007-11-19
申请人： Joon-Hee Lee
发明人： Joon-Hee Lee
IPC分类号： B32B7/02 , B32B27/06
CPC分类号： B32B27/34 , Y10T428/2495 , Y10T428/2933
摘要： The present invention relates to an insulated electric wire. The insulated electric wire according to the present invention includes a high adhesion resin layer made of a polyamideimide resin containing a compound having a polar group in a molecular structure of an insulation material; and a high flexibility resin layer provided on the high adhesion resin layer. The present invention advantageously improves adherence between a polyamideimide resin and a conductor, and provides adhesive strength with the conductor to improve flexibility of the insulated electric wire and at the same time to improve flexibility of an insulator without deterioration of heat resistance of the insulator.
摘要翻译：绝缘电线本发明涉及绝缘电线。根据本发明的绝缘电线包括由包含绝缘材料的分子结构中具有极性基团的化合物的聚酰胺酰亚胺树脂制成的高粘合性树脂层; 以及设置在高粘合性树脂层上的高弹性树脂层。本发明有利地提高了聚酰胺酰亚胺树脂与导体之间的粘附性，并且与导体提供粘合强度以提高绝缘电线的柔性，同时提高绝缘体的柔性，同时绝缘体的耐热性也不会降低。

37. 发明授权

US07414202B2 Insulated electric wire with partial discharge resistance and composition for manufacturing the same 有权
标题翻译：具有局部放电电阻的绝缘电线及其制造用组合物
公开(公告)号：US07414202B2
公开(公告)日：2008-08-19
申请号：US11703117
申请日：2007-02-05
申请人： Joon-Hee Lee , Ki-Hong Park
发明人： Joon-Hee Lee , Ki-Hong Park
IPC分类号： H01B7/00
CPC分类号： H01B3/306 , H01B3/421
摘要： Disclosed are an insulated electric wire with partial discharge resistance and a composition for manufacturing the same. The insulated electric wire with partial discharge resistance according to the present invention includes an insulating base resin constituting a basic material of an insulated electric wire; an inorganic insulator included at a content of 5 to 40 parts by weight on the basis of 100 parts by weight of the insulating base resin; and a rubbery modifier included at a content of 0.1 to 30 parts by weight on the basis of 100 parts by weight of the insulating base resin to improve flexibility of an insulated electric wire. The insulated electric wire with partial discharge resistance of the present invention may be useful to prevent occurrence of cracks caused by winding of an insulated electric wire since the insulated electric wire has a sufficient partial discharge resistance and also enhances sufficient physical properties such as flexibility, pliability, bendability, elongation, etc. to maintain an electrically insulating property intactly by dispersing a stress, applied from an external force, by means of a rubber component attached to an end thereof.
摘要翻译：公开了一种具有部分放电电阻的绝缘电线及其制造用组合物。根据本发明的具有耐放电电阻的绝缘电线包括构成绝缘电线的基本材料的绝缘基础树脂; 基于绝缘基础树脂100重量份含有5至40重量份的无机绝缘体; 和含有0.1-30重量份的橡胶状改性剂，以100重量份的绝缘基础树脂为基础，以提高绝缘电线的柔韧性。本发明的具有耐放电电阻的绝缘电线可用于防止由于绝缘电线具有足够的局部放电电阻而引起的由绝缘电线缠绕引起的裂纹的发生，并且还增强了足够的物理性能，如柔韧性，柔韧性，弯曲性，伸长率等，通过分散由外力施加的应力，通过附着在其一端的橡胶部件来完整地保持电绝缘性。

38. 发明授权

US07394696B2 NAND type non-volatile memory device and method of forming the same 有权
公开(公告)号：US07394696B2
公开(公告)日：2008-07-01
申请号：US11646164
申请日：2006-12-27
申请人： Joon-Hee Lee , Su-In Baek
发明人： Joon-Hee Lee , Su-In Baek
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A NAND type non-volatile memory device and a method for forming the same. Well bias lines are disposed substantially parallel to other wiring lines at equal intervals. Active regions that are electrically connected to the well bias line are disposed substantially parallel to other active regions at the same equal intervals. As a result, continuity and repeatability in patterns may be maintained and pattern defects may be minimized or prevented.

39. 发明申请

US20080005631A1 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US20080005631A1
公开(公告)日：2008-01-03
申请号：US11811551
申请日：2007-06-11
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G11C29/08
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of data bits from a plurality of memory blocks. In addition, each comparison unit outputs data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个数据位。此外，每个比较单元从相应的存储器芯片内的一个存储块输出数据位。

40. 发明申请

US20050216809A1 Memory module with parallel testing 失效
标题翻译：内存模块并行测试
公开(公告)号：US20050216809A1
公开(公告)日：2005-09-29
申请号：US11086059
申请日：2005-03-22
申请人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
发明人： Youn-Cheul Kim , Hee-Joo Choi , Kae-Won Ha , Joon-Hee Lee
IPC分类号： G01R31/28 , G06F11/00 , G06F12/16 , G11C29/00 , G11C29/28 , G11C29/34 , G11C29/40
CPC分类号： G11C29/40 , G11C29/28 , G11C2029/2602
摘要： Each memory chip of a memory module tests a total of N data bits from X memory blocks for efficient testing and outputs N/X test data bits from one of the memory blocks. A memory module includes a plurality of memory chips and a plurality of comparison units. Each comparison unit is disposed within a respective memory chip for testing a plurality of test data bits from a plurality of memory blocks. In addition, each comparison unit outputs test data bits from one of the memory blocks within the respective memory chip.
摘要翻译：存储器模块的每个存储器芯片测试来自X个存储器块的总共N个数据位用于有效测试，并从其中一个存储器块输出N / X个测试数据位。存储器模块包括多个存储器芯片和多个比较单元。每个比较单元设置在相应的存储器芯片内，用于从多个存储器块测试多个测试数据位。此外，每个比较单元从相应的存储器芯片内的一个存储器块输出测试数据位。

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