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31. 发明授权

US09335993B2 Convert from zoned format to decimal floating point format 有权
公开(公告)号：US09335993B2
公开(公告)日：2016-05-10
申请号：US13339791
申请日：2011-12-29
申请人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, Jr. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
发明人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, Jr. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/30
CPC分类号： G06F9/30181 , G06F7/483 , G06F9/3001 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/3016
摘要： Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

32. 发明申请

US20130173891A1 CONVERT FROM ZONED FORMAT TO DECIMAL FLOATING POINT FORMAT 有权
公开(公告)号：US20130173891A1
公开(公告)日：2013-07-04
申请号：US13339791
申请日：2011-12-29
申请人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, JR. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
发明人： Steven R. Carlough , Reid T. Copeland , Charles W. Gainey, JR. , Marcel Mitran , Eric M. Schwarz , Timothy J. Slegel
IPC分类号： G06F9/302
CPC分类号： G06F9/30181 , G06F7/483 , G06F9/3001 , G06F9/30025 , G06F9/30036 , G06F9/30098 , G06F9/30112 , G06F9/3016
摘要： Machine instructions, referred to herein as a long Convert from Zoned instruction (CDZT) and extended Convert from Zoned instruction (CXZT), are provided that read EBCDIC or ASCII data from memory, convert it to the appropriate decimal floating point format, and write it to a target floating point register or floating point register pair. Further, machine instructions, referred to herein as a long Convert to Zoned instruction (CZDT) and extended Convert to Zoned instruction (CZXT), are provided that convert a decimal floating point (DFP) operand in a source floating point register or floating point register pair to EBCDIC or ASCII data and store it to a target memory location.

33. 发明授权

US07712076B2 Register indirect access of program floating point registers by millicode 失效
标题翻译：通过millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US07712076B2
公开(公告)日：2010-05-04
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/44
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

34. 发明申请

US20080126759A1 Register Indirect Access of Program Floating Point Registers by Millicode 失效
标题翻译：通过Millicode寄存器间接访问程序浮点寄存器
公开(公告)号：US20080126759A1
公开(公告)日：2008-05-29
申请号：US11531301
申请日：2006-09-13
申请人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
发明人： Steven R. Carlough , Mark S. Farrell , Eric M. Schwarz , Timothy J. Slegel , Charles F. Webb
IPC分类号： G06F9/302
CPC分类号： G06F9/3017 , G06F9/35
摘要： Complex floating point instructions are executed under millicode control when it is not cost effective to implement its function in hardware. One of the disadvantages to executing complex instructions using millicode routines is that determining and accessing the instructions operands are costly for millicode performance. To determine what the source and target location are, the instruction text is parsed. Furthermore the millicode instruction stream must be modified to access the operand data from and write the result to the program registers specified by the complex floating point instruction. The invention overcomes these disadvantages by providing millicode with register indirect access to the program floating point registers.
摘要翻译：当在硬件中实现其功能不具有成本效益时，复杂的浮点指令在毫秒控制下执行。使用millicode例程执行复杂指令的一个缺点是确定和访问指令操作数对于millicode性能来说是昂贵的。要确定源和目标位置是什么，解释说明文本。此外，必须修改millicode指令流以访问操作数数据，并将结果写入由复杂浮点指令指定的程序寄存器。本发明通过向编程浮点寄存器提供寄存器间接访问的毫代码来克服这些缺点。

35. 发明授权

US09229722B2 Major branch instructions with transactional memory 有权
公开(公告)号：US09229722B2
公开(公告)日：2016-01-05
申请号：US13362513
申请日：2012-01-31
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/30 , G06F9/40 , G06F9/46 , G06F9/38 , G06F9/32 , G06F9/52
CPC分类号： G06F9/3804 , G06F9/3005 , G06F9/30145 , G06F9/322 , G06F9/3842 , G06F9/3851 , G06F9/46 , G06F9/466 , G06F9/467 , G06F9/528
摘要： Major branch instructions are provided that enable execution of a computer program to branch from one segment of code to another segment of code. These instructions also create a new stream of processing at the other segment of code enabling execution of the other segment of code to be performed in parallel with the segment of code from which the branch was taken. In one example, the other stream of processing starts a transaction for processing instructions of the other stream of processing.

36. 发明授权

US09021493B2 Management of resources within a computing environment 有权
公开(公告)号：US09021493B2
公开(公告)日：2015-04-28
申请号：US13615704
申请日：2012-09-14
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/46 , G06F9/38 , G06F9/50
CPC分类号： G06F9/5038 , G06F9/38 , G06F9/45533 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F9/5016 , G06F9/5077 , G06F2009/45591 , G06F2209/483 , G06F2209/5021 , G06F2209/504 , G06F2209/507 , G06F2209/508 , Y02B70/30 , Y02D10/22
摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).

37. 发明申请

US20140082625A1 MANAGEMENT OF RESOURCES WITHIN A COMPUTING ENVIRONMENT 有权
标题翻译：在计算环境中的资源管理
公开(公告)号：US20140082625A1
公开(公告)日：2014-03-20
申请号：US13615704
申请日：2012-09-14
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F9/50
CPC分类号： G06F9/5038 , G06F9/38 , G06F9/45533 , G06F9/4881 , G06F9/50 , G06F9/5011 , G06F9/5016 , G06F9/5077 , G06F2009/45591 , G06F2209/483 , G06F2209/5021 , G06F2209/504 , G06F2209/507 , G06F2209/508 , Y02B70/30 , Y02D10/22
摘要： Resources in a computing environment are managed, for example, by a hardware controller controlling dispatching of resources from one or more pools of resources to be used in execution of threads. The controlling includes conditionally dispatching resources from the pool(s) to one or more low-priority threads of the computing environment based on current usage of resources in the pool(s) relative to an associated resource usage threshold. The management further includes monitoring resource dispatching from the pool(s) to one or more high-priority threads of the computing environment, and based on the monitoring, dynamically adjusting the resource usage threshold used in the conditionally dispatching of resources from the pool(s) to the low-priority thread(s).
摘要翻译：计算环境中的资源例如通过硬件控制器进行管理，硬件控制器控制从用于执行线程的一个或多个资源池中调度资源。所述控制包括基于所述池中的资源相对于相关联的资源使用阈值的当前使用情况，将资源从所述池有条件地调度到所述计算环境的一个或多个低优先级线程。该管理还包括监视从该池到该计算环境的一个或多个高优先级线程的资源调度，并且基于该监视，动态地调整在从池中有条件地分派资源中使用的资源使用阈值）到低优先级线程。

38. 发明申请

US20140019803A1 HARDWARE RECOVERY IN MULTI-THREADED PROCESSOR 有权
标题翻译：多线程处理器中的硬件恢复
公开(公告)号：US20140019803A1
公开(公告)日：2014-01-16
申请号：US13548448
申请日：2012-07-13
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F11/14
CPC分类号： G06F11/1479 , G06F11/1438
摘要： A computer system includes a simultaneous multi-threading processor and memory in operable communication with the processor. The processor is configured to perform a method including running multiple threads simultaneously, detecting a hardware error in one or more hardware structures of the processing circuit, and identifying one or more victim threads of the multiple threads. The processor is further configured to identify a plurality of hardware structures associated with execution of the one or more victim threads, isolate the one or more victim threads from the rest of the multiple threads by preventing access to the plurality of hardware structures by the multiple threads, flush the one or more victim threads by resetting hardware states of the plurality of hardware structures, and restore the one or more victim threads by restoring the plurality of hardware structures to a known safe state.
摘要翻译：计算机系统包括同时多线程处理器和与处理器可操作地通信的存储器。处理器被配置为执行包括同时运行多个线程的方法，检测处理电路的一个或多个硬件结构中的硬件错误，以及识别多个线程的一个或多个受害者线程。所述处理器还被配置为识别与所述一个或多个受害者线程的执行相关联的多个硬件结构，通过所述多个线程阻止对所述多个硬件结构的访问来将所述一个或多个受害者线程与所述多个线程的其余部分隔离通过重置多个硬件结构的硬件状态来刷新一个或多个受害者线程，并通过将多个硬件结构恢复到已知的安全状态来恢复一个或多个受害者线程。

39. 发明申请

US20130191599A1 CACHE SET REPLACEMENT ORDER BASED ON TEMPORAL SET RECORDING 有权
标题翻译：基于时间设置记录的缓存设置替换顺序
公开(公告)号：US20130191599A1
公开(公告)日：2013-07-25
申请号：US13354894
申请日：2012-01-20
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , Brian R. Prasky , Chung-Lung K. Shum
IPC分类号： G06F12/12
CPC分类号： G06F12/0875 , G06F12/126
摘要： A technique is provided for cache management of a cache. The processing circuit determines a miss count and a hit position field during a previous execution of an instruction requesting that a data element be stored in a cache. The miss count and the hit position field are stored for a data element corresponding to an instruction that requests storage of the data element. The processing circuit places the data element in a hierarchical order based on the miss count and/or the hit position field. The hit position field includes a hierarchical position related to the data element in the cache.
摘要翻译：提供了用于高速缓存的高速缓存管理的技术。处理电路在先前执行请求数据元素存储在高速缓存中的指令期间确定未命中和命中位置字段。针对与请求存储数据元素的指令相对应的数据元素存储未命中和命中位置字段。处理电路基于错过次数和/或命中位置字段将数据元素放置成分层次序。命中位置字段包括与缓存中的数据元素相关的分层位置。

40. 发明授权

US07412476B2 Decimal multiplication for superscaler processors 失效
标题翻译：超标量处理器的十进制乘法
公开(公告)号：US07412476B2
公开(公告)日：2008-08-12
申请号：US11460296
申请日：2006-07-27
申请人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
发明人： Fadi Y. Busaba , Steven R. Carlough , Christopher A. Krygowski , John G. Rell, Jr.
IPC分类号： G06F7/523
CPC分类号： G06F9/3001 , G06F7/496
摘要： A method for decimal multiplication in a superscaler processor comprising: obtaining a first operand and a second operand; establishing a multiplier and an effective multiplicand from the first operand and the second operand; and generating and accumulating a partial product term every two cycles. The partial product terms are created from the effective multiplicand and multiples of the multiplier, where the effective multiplicand is stored in a first register file, the multiples being ones times the effective multiplier, two times the effective multiplier, four times the effective multiplier and eight times the effective multiplier and the partial product terms are added to an accumulation of previous partial product terms shifted one digit right such that a digit shifted off is preserved as a result digit.
摘要翻译：一种用于在超标量处理器中进行十进制相乘的方法，包括：获得第一操作数和第二操作数; 从第一个操作数和第二个操作数建立乘数和有效的被乘数; 并且每两个周期产生和累积部分乘积项。部分乘积项是从乘法器的有效乘数和乘数创建的，其中有效被乘数存储在第一个寄存器文件中，倍数是有效乘数的倍数，有效乘数的两倍，有效乘数的四倍和八倍乘以有效乘数和部分乘积项添加到前一个部分乘积项的累积中，该乘积项被移位一位数字，使得数字移位被保留为结果位。

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