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31. 发明授权

US07581152B2 Fault free store data path for software implementation of redundant multithreading environments 有权
标题翻译：无故障存储数据路径，用于冗余多线程环境的软件实现
公开(公告)号：US07581152B2
公开(公告)日：2009-08-25
申请号：US11022600
申请日：2004-12-22
申请人： Shubhendu S. Mukherjee , Robert Cohn
发明人： Shubhendu S. Mukherjee , Robert Cohn
IPC分类号： G01R31/28
CPC分类号： G06F11/1497
摘要： A method for a fault free store data path in a software implementation of redundant multithreading environments is described. In one embodiment, after a check is performed by a hardware/software checker, the processor still needs to ensure that the data just checked reaches protected memory without any faults. The present implementation provides sufficient redundant information along the path of a store from register read to commit, such that it may detect any single bit upset error in the path.
摘要翻译：描述了冗余多线程环境的软件实现中的无故障存储数据路径的方法。在一个实施例中，在由硬件/软件检查器执行检查之后，处理器仍然需要确保刚刚检查的数据到达受保护的存储器而没有任何故障。本实施例提供了从寄存器读取到提交的存储路径中的足够的冗余信息，使得其可以检测到路径中的任何单个位失真错误。

32. 发明授权

US07529118B2 Generalized interlocked register cell (GICE) 有权
标题翻译：通用互锁寄存器单元（GICE）
公开(公告)号：US07529118B2
公开(公告)日：2009-05-05
申请号：US11729197
申请日：2007-03-28
申请人： Wayne Burleson , Shubhendu S. Mukherjee , Vinod Ambrose , Daniel E. Holcomb
发明人： Wayne Burleson , Shubhendu S. Mukherjee , Vinod Ambrose , Daniel E. Holcomb
IPC分类号： G11C11/00
CPC分类号： G11C11/41 , G11C11/4125
摘要： A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.
摘要翻译：提供一种存储元件，其包括使用互补金属氧化物半导体（CMOS）技术的容错存储元件族。存储器元件提供任意级别的冗余，允许由于粒子命中而导致的多个单事件容错。存储器元件可以用在诸如高速缓存和寄存器文件的存储器阵列中，以及在数据路径和控制结构中找到的时钟寄存器和锁存器。

33. 发明申请

US20080239793A1 Generalized Interlocked Register Cell (GICE) 有权
标题翻译：广义联锁寄存器单元（GICE）
公开(公告)号：US20080239793A1
公开(公告)日：2008-10-02
申请号：US11729197
申请日：2007-03-28
申请人： Wayne Burleson , Shubhendu S. Mukherjee , Vinod Ambrose , Daniel E. Holcomb
发明人： Wayne Burleson , Shubhendu S. Mukherjee , Vinod Ambrose , Daniel E. Holcomb
IPC分类号： G11C11/06
CPC分类号： G11C11/41 , G11C11/4125
摘要： A memory element which includes a family of fault-tolerant storage elements using complementary metal-oxide-semiconductor (CMOS) technology is provided. The memory element provides arbitrary levels of redundancy, allowing the tolerance of multiple single event upsets due to particle hits. The memory element may be used in memory arrays such as caches and register files, and clocked registers and latches found in data path and control structures.
摘要翻译：提供一种存储元件，其包括使用互补金属氧化物半导体（CMOS）技术的容错存储元件族。存储器元件提供任意级别的冗余，允许由于粒子命中而导致的多个单事件容错。存储器元件可以用在诸如高速缓存和寄存器文件的存储器阵列中，以及在数据路径和控制结构中找到的时钟寄存器和锁存器。

34. 发明授权

US06854051B2 Cycle count replication in a simultaneous and redundantly threaded processor 有权
标题翻译：同时和冗余线程处理器中的循环计数复制
公开(公告)号：US06854051B2
公开(公告)日：2005-02-08
申请号：US09839459
申请日：2001-04-19
申请人： Shubhendu S. Mukherjee
发明人： Shubhendu S. Mukherjee
IPC分类号： G06F11/14 , G06F9/38 , G06F9/44 , G06F9/54
CPC分类号： G06F11/1405 , G06F11/1497
摘要： A pipelined, simultaneous and redundantly threaded (“SRT”) processor comprising, among other components, load/store units configured to perform load and store operations to or from data locations such as a data cache and data registers and a cycle counter configured to keep a running count of processor clock cycles. The processor is configured to detect transient faults during program execution by executing instructions in at least two redundant copies of a program thread and wherein false errors caused by incorrectly replicating cycle count values in the redundant program threads are avoided by implementing a cycle count queue for storing the actual values fetched by read cycle count instructions in the first program thread. The load/store units then access the cycle count queue and not the cycle counter to fetch cycle count values in response to read cycle count instructions in the second program thread.
摘要翻译：一种流水线式，同时和冗余线程（“SRT”）处理器，其包括被配置为对诸如数据高速缓存和数据寄存器之类的数据位置执行加载和存储操作的加载/存储单元，以及被配置为保持处理器时钟周期的运行计数。处理器被配置为通过在程序线程的至少两个冗余副本中执行指令来检测程序执行期间的瞬态故障，并且其中通过实施用于存储的循环计数队列来避免冗余程序线程中不正确地复制循环计数值引起的错误错误在第一个程序线程中通过读周期计数指令获取的实际值。加载/存储单元然后访问周期计数队列，而不是周期计数器，以响应第二个程序线程中的读周期计数指令来提取周期计数值。

35. 发明授权

US06823473B2 Simultaneous and redundantly threaded processor uncached load address comparator and data value replication circuit 有权
标题翻译：同时冗余线程处理器未加载地址比较器和数据复制电路
公开(公告)号：US06823473B2
公开(公告)日：2004-11-23
申请号：US09839626
申请日：2001-04-19
申请人： Shubhendu S. Mukherjee
发明人： Shubhendu S. Mukherjee
IPC分类号： G06F1100
CPC分类号： G06F11/1497 , G06F11/141
摘要： A simultaneous and redundantly threaded, pipelined processor executes the same set of instructions simultaneously as two separate threads to provide fault tolerance. One thread is processed ahead of the other thread so that the instructions in one thread are processed through the processor's pipeline ahead of the corresponding instructions from the other thread. The thread, whose instructions are processed earlier, places its uncached reads in a read queue. Subsequently, the second thread places its uncached reads in the read queue. A compare circuit periodically scans the read queue for matching uncached read instructions. If otherwise matching instructions differ in their target address, then a fault has occurred in the processing and the compare circuits initiates fault recovery. If comparison of the two instructions reveals they are identical, the compare circuit allows only a single uncached read instruction to pass to the system main memory. The data returned from the uncached read is replicated and passed to each thread. In this way, transient faults are detected with a minimum amount of hardware overhead and independent of differences in the actual order of program execution or differences in branch speculation.
摘要翻译：同时和冗余线程的流水线处理器同时执行同一组指令，作为两个单独的线程提供容错。一个线程在另一个线程之前被处理，使得一条线程中的指令在来自另一线程的相应指令之前通过处理器的管线进行处理。先前处理其指令的线程将其未读取的读取放置在读取队列中。随后，第二个线程将其未读取的读取放置在读取队列中。比较电路周期性地扫描读取队列以匹配未读取的读取指令。如果其他匹配指令的目标地址不同，则处理中发生故障，比较电路会启动故障恢复。如果两个指令的比较表明它们是相同的，则比较电路只允许单个未读取的指令传递给系统主存储器。从未缓存的读取返回的数据被复制并传递给每个线程。以这种方式，以最小量的硬件开销检测瞬态故障，并且独立于程序执行的实际顺序或分支推测的差异。

36. 发明授权

US08291394B2 Method and apparatus for detecting transient faults via dynamic binary translation 有权
标题翻译：通过动态二进制翻译检测瞬态故障的方法和装置
公开(公告)号：US08291394B2
公开(公告)日：2012-10-16
申请号：US13135712
申请日：2011-07-13
申请人： George A. Reis , Robert Cohn , Shubhendu S. Mukherjee
发明人： George A. Reis , Robert Cohn , Shubhendu S. Mukherjee
IPC分类号： G06F9/45
CPC分类号： G06F8/52 , G06F8/53 , G06F11/008
摘要： A method for detecting transient fault includes translating binary code to an intermediate language code. An instruction of interest in the intermediate language code is identified. Reliability instructions are inserted in the intermediate language code to validate values from the instruction of interest. The intermediate language code is translated to binary code. Other embodiments are described and claimed.
摘要翻译：用于检测瞬态故障的方法包括将二进制代码转换为中间语言代码。识别中间语言代码感兴趣的指令。可靠性指令插入中间语言代码以验证感兴趣的指令中的值。中间语言代码被翻译成二进制代码。描述和要求保护其他实施例。

37. 发明授权

US07954038B2 Fault detection 有权
标题翻译：故障检测
公开(公告)号：US07954038B2
公开(公告)日：2011-05-31
申请号：US11648853
申请日：2006-12-29
申请人： Paul Racunas , Srilatha Manne , Kypros Constantinides , Shubhendu S. Mukherjee
发明人： Paul Racunas , Srilatha Manne , Kypros Constantinides , Shubhendu S. Mukherjee
IPC分类号： G11C29/00
CPC分类号： G06F11/0751 , G06F11/0721 , G06F11/1407
摘要： Methods and apparatus to efficiently detect faults are described. In an embodiment, an encoded value may be generated based on a portion of an instruction address and a portion of a corresponding result value. The encoded value may be used to determine whether an entry corresponding to the encoded value is absent from a screening storage unit. Other embodiments are also described.
摘要翻译：描述了有效检测故障的方法和设备。在一个实施例中，可以基于指令地址的一部分和相应结果值的一部分来生成编码值。编码值可以用于确定与筛选存储单元是否不存在与编码值相对应的条目。还描述了其它实施例。

38. 发明申请

US20100169582A1 Obtaining data for redundant multithreading (RMT) execution 有权
标题翻译：获取冗余多线程（RMT）执行的数据
公开(公告)号：US20100169582A1
公开(公告)日：2010-07-01
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08 , G06F12/00 , G06F9/46
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。描述和要求保护其他实施例。

39. 发明授权

US09081688B2 Obtaining data for redundant multithreading (RMT) execution 有权
标题翻译：获取冗余多线程（RMT）执行的数据
公开(公告)号：US09081688B2
公开(公告)日：2015-07-14
申请号：US12317801
申请日：2008-12-30
申请人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
发明人： Glenn J. Hinton , Steven E. Raasch , Sebastien Hily , John G. Holm , Ronak Singhal , Avinash Sodani , Deborah T. Marr , Shubhendu S. Mukherjee , Arijit Biswas , Adrian C. Moga
IPC分类号： G06F12/08
CPC分类号： G06F12/0842 , G06F12/0817
摘要： In one embodiment, the present invention includes a method for providing a cache block in an exclusive state to a first cache and providing the same cache block in the exclusive state to a second cache when cores accessing the two caches are executing redundant threads. Other embodiments are described and claimed.
摘要翻译：在一个实施例中，本发明包括一种用于向第一高速缓存提供处于独占状态的高速缓存块的方法，并且当访问两个高速缓存的核心正在执行冗余线程时，以独占状态将相同的高速缓存块提供给第二高速缓存。描述和要求保护其他实施例。

40. 发明授权

US07747897B2 Method and apparatus for lockstep processing on a fixed-latency interconnect 有权
标题翻译：在固定延迟互连上进行锁步处理的方法和装置
公开(公告)号：US07747897B2
公开(公告)日：2010-06-29
申请号：US11282213
申请日：2005-11-18
申请人： Paul B. Racunas , Matthew Mattina , George Z. Chrysos , Shubhendu S. Mukherjee
发明人： Paul B. Racunas , Matthew Mattina , George Z. Chrysos , Shubhendu S. Mukherjee
IPC分类号： G06F11/00 , G06F17/00 , G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F11/1683 , G06F11/1637
摘要： Methods of operating two or more devices in lockstep by generating requests at each device, comparing the requests, and forwarding matching requests to a servicing node are described and claimed. A redundant execution system using the methods is also described and claimed.
摘要翻译：描述并要求保护在每个设备上生成请求，比较请求以及将匹配请求转发到服务节点的锁步骤中的两个或多个设备的操作方法。还描述并声明了使用该方法的冗余执行系统。

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