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31. 发明申请

US20100311250A1 THIN SUBSTRATE FABRICATION USING STRESS-INDUCED SUBSTRATE SPALLING 有权
标题翻译：使用应力诱导基板薄化薄基板制造
公开(公告)号：US20100311250A1
公开(公告)日：2010-12-09
申请号：US12784688
申请日：2010-05-21
申请人： Stephen W. Bedell , Keith E. Fogel , Paul A. Lauro , Devendra Sadana
发明人： Stephen W. Bedell , Keith E. Fogel , Paul A. Lauro , Devendra Sadana
IPC分类号： H01L21/30
CPC分类号： H01L31/0304 , H01L21/20 , H01L21/76254 , H01L31/03762 , H01L31/0725 , H01L31/074 , H01L31/075 , H01L31/076 , H01L31/184 , H01L31/1892 , H01L31/20 , Y02E10/548
摘要： A method for manufacturing a thin film direct bandgap semiconductor active solar cell device comprises providing a source substrate having a surface and disposing on the surface a stress layer having a stress layer surface area in contact with and bonded to the surface of the source substrate. Operatively associating a handle foil with the stress layer and applying force to the handle foil separates the stress layer from the source substrate, and leaves a portion of the source substrate on the stress layer surface substantially corresponding to the area in contact with the surface of the source substrate. The portion is less thick than the source layer. The stress layer thickness is below that which results in spontaneous spalling of the source substrate. The source substrate may comprise an inorganic single crystal or polycrystalline material such as Si, Ge, GaAs, SiC, sapphire, or GaN. In one embodiment the stress layer comprises a flexible material.
摘要翻译：一种制造薄膜直接带隙半导体活性太阳能电池器件的方法，包括提供具有表面的源极衬底，并且在表面上设置应力层，该应力层具有与源极衬底的表面接触并且结合到源极衬底的表面。将手柄箔与应力层操作地相关联并且向手柄箔施加力将应力层与源衬底分离，并将源衬底的一部分留在应力层表面上，基本上对应于与表面相接触的区域源底物。该部分的厚度不如源层厚。应力层厚度低于导致源底材自发剥落的厚度。源极衬底可以包括无机单晶或多晶材料，例如Si，Ge，GaAs，SiC，蓝宝石或GaN。在一个实施例中，应力层包括柔性材料。

32. 发明授权

US07679141B2 High-quality SGOI by annealing near the alloy melting point 失效
标题翻译：高品质SGOI通过在合金熔点附近退火
公开(公告)号：US07679141B2
公开(公告)日：2010-03-16
申请号：US12027561
申请日：2008-02-07
申请人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Anthony G. Domenicucci , Keith E. Fogel , Richard J. Murphy , Devendra K. Sadana
IPC分类号： H01L31/392
CPC分类号： H01L21/26506 , H01L21/324 , H01L21/7624 , H01L21/76254 , H01L29/1054
摘要： A method of forming a low-defect, substantially relaxed SiGe-on-insulator substrate material is provided. The method includes first forming a Ge-containing layer on a surface of a first single crystal Si layer which is present atop a barrier layer that is resistant to Ge diffusion. A heating step is then performed at a temperature that approaches the melting point of the final SiGe alloy and retards the formation of stacking fault defects while retaining Ge. The heating step permits interdiffusion of Ge throughout the first single crystal Si layer and the Ge-containing layer thereby forming a substantially relaxed, single crystal SiGe layer atop the barrier layer. Moreover, because the heating step is carried out at a temperature that approaches the melting point of the final SiGe alloy, defects that persist in the single crystal SiGe layer as a result of relaxation are efficiently annihilated therefrom. In one embodiment, the heating step includes an oxidation process that is performed at a temperature from about 1230° to about 1320° C. for a time period of less than about 2 hours. This embodiment provides SGOI substrate that have minimal surface pitting and reduced crosshatching.
摘要翻译：提供一种形成低缺陷，基本上松弛的绝缘体上硅衬底材料的方法。该方法包括首先在耐Ge扩散的阻挡层上存在的第一单晶Si层的表面上形成含Ge层。然后在接近最终SiGe合金的熔点的温度下进行加热步骤，并且在保留Ge的同时延缓层叠缺陷缺陷的形成。加热步骤允许Ge遍及第一单晶Si层和含Ge层的相互扩散，从而在阻挡层顶部形成基本松弛的单晶SiGe层。此外，由于加热步骤在接近最终SiGe合金的熔点的温度下进行，所以由于弛豫而在单晶SiGe层中持续存在的缺陷被有效地湮灭。在一个实施方案中，加热步骤包括氧化过程，其在约1230℃至约1320℃的温度下进行约少于约2小时的时间。该实施例提供具有最小表面点蚀和减少的交叉阴影的SGOI衬底。

33. 发明申请

US20090186455A1 DISPOSABLE METALLIC OR SEMICONDUCTOR GATE SPACER 失效
标题翻译：可拆卸金属或半导体门间隔
公开(公告)号：US20090186455A1
公开(公告)日：2009-07-23
申请号：US12016326
申请日：2008-01-18
申请人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
发明人： Stephen W. Bedell , Michael Chudzik , William K. Henson , Naim Moumen , Vijay Narayanan , Devendra K. Sadana , Kathryn T. Schonenberg , Ghavam Shahidi
IPC分类号： H01L21/8238
CPC分类号： H01L29/7847 , H01L21/324 , H01L21/823807 , H01L21/823864 , H01L29/665 , H01L29/6653 , H01L29/6656
摘要： A disposable spacer is formed directly on or in close proximity to the sidewalls of a gate electrode and a gate dielectric. The disposable spacer comprises a material that scavenges oxygen such as a metal, a metal nitride, or a semiconductor material having high reactivity with oxygen. The disposable gate spacer absorbs any oxygen during subsequent high temperature processing such as a stress memorization anneal. A metal is deposited over, and reacted with, the gate electrode and source and drain regions to form metal semiconductor alloy regions. The disposable gate spacer is subsequently removed selective to the metal semiconductor alloy regions. A porous or non-porous low-k dielectric material is deposited to provide a low parasitic capacitance between the gate electrode and the source and drain regions. The gate dielectric maintains the original dielectric constant since the disposable gate spacer prevents absorption of additional oxygen during high temperature processes.
摘要翻译：一次性间隔物直接形成在栅极电极和栅极电介质的侧壁上或紧邻栅电极的侧壁上。一次性间隔物包括清除氧的材料，例如金属，金属氮化物或具有高氧反应性的半导体材料。一次性栅极间隔件在随后的高温处理例如应力记忆退火期间吸收任何氧气。将金属沉积在栅电极和源极和漏极区上并与其反应以形成金属半导体合金区域。一次性栅极间隔物随后被选择性地移除到金属半导体合金区域。沉积多孔或非多孔低k电介质材料以在栅极电极和源极和漏极区域之间提供低的寄生电容。栅极电介质保持原始介电常数，因为一次性栅极间隔物可防止在高温过程中吸收额外的氧。

34. 发明申请

US20080296634A1 STRUCTURE AND METHOD FOR MANUFACTURING STRAINED SILICON DIRECTLY-ON-INSULATOR SUBSTRATE WITH HYBRID CRYSTALLINE ORIENTATION AND DIFFERENT STRESS LEVELS 失效
标题翻译：用混合晶体取向和不同应力水平制造具有应力的硅直接绝缘体衬底的结构和方法
公开(公告)号：US20080296634A1
公开(公告)日：2008-12-04
申请号：US12192573
申请日：2008-08-15
申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
发明人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
IPC分类号： H01L29/04 , H01L29/00
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

35. 发明授权

US07423303B2 Strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels 有权
标题翻译：应变硅直接绝缘体上的衬底，具有杂化晶体取向和不同的应力水平
公开(公告)号：US07423303B2
公开(公告)日：2008-09-09
申请号：US11830464
申请日：2007-07-30
申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
发明人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
IPC分类号： H01L29/786
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

36. 发明申请

US20080164493A1 Structures containing electrodeposited germanium and methods for their fabrication 失效
标题翻译：含有电沉积锗的结构及其制造方法
公开(公告)号：US20080164493A1
公开(公告)日：2008-07-10
申请号：US11620224
申请日：2007-01-05
申请人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
发明人： Stephen W. Bedell , Hariklia Deligianni , Qiang Huang , Lubomyr T. Romankiw , Devendra K. Sadana , Katherine L. Saenger
IPC分类号： H01L29/778 , H01L21/208
CPC分类号： H01L21/823807 , H01L21/0237 , H01L21/02532 , H01L21/02628 , H01L21/02636 , H01L21/02639 , H01L21/28255 , H01L29/1054 , H01L29/78
摘要： Methods for electrodepositing germanium on various semiconductor substrates such as Si, Ge, SiGe, and GaAs are provided. The electrodeposited germanium can be formed as a blanket or patterned film, and may be crystallized by solid phase epitaxy to the orientation of the underlying semiconductor substrate by subsequent annealing. These plated germanium layers may be used as the channel regions of high-mobility channel field effect transistors (FETs) in complementary metal oxide semiconductor (CMOS) circuits.
摘要翻译：提供了在诸如Si，Ge，SiGe和GaAs的各种半导体衬底上电沉积锗的方法。电沉积锗可以形成为覆盖或图案化的膜，并且可以通过后续退火使固相外延结晶到下面的半导体衬底的取向。这些电镀锗层可以用作互补金属氧化物半导体（CMOS）电路中的高迁移率沟道场效应晶体管（FET）的沟道区。

37. 发明授权

US07271043B2 Method for manufacturing strained silicon directly-on-insulator substrate with hybrid crystalline orientation and different stress levels 失效
标题翻译：用于制造具有混合晶体取向和不同应力水平的应变硅绝缘体上基板的方法
公开(公告)号：US07271043B2
公开(公告)日：2007-09-18
申请号：US11037622
申请日：2005-01-18
申请人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
发明人： Huilong Zhu , Bruce B. Doris , Huajie Chen , Patricia M. Mooney , Stephen W. Bedell
IPC分类号： H01L21/8238
CPC分类号： H01L27/1203 , H01L21/76254 , H01L21/823807 , H01L21/823878 , H01L21/84
摘要： The present invention provides a strained Si directly on insulator (SSDOI) substrate having multiple crystallographic orientations and a method of forming thereof. Broadly, but in specific terms, the inventive SSDOI substrate includes a substrate; an insulating layer atop the substrate; and a semiconducting layer positioned atop and in direct contact with the insulating layer, the semiconducting layer comprising a first strained Si region and a second strained Si region; wherein the first strained Si region has a crystallographic orientation different from the second strained Si region and the first strained Si region has a crystallographic orientation the same or different from the second strained Si region. The strained level of the first strained Si region is different from that of the second strained Si region.
摘要翻译：本发明提供了具有多个结晶取向的应变Si直接绝缘体（SSDOI）基板及其形成方法。广义上，但是具体来说，本发明的SSDOI基板包括基板; 衬底顶部的绝缘层; 以及位于顶部并与绝缘层直接接触的半导体层，所述半导体层包括第一应变Si区和第二应变Si区; 其中所述第一应变Si区具有不同于所述第二应变Si区的晶体取向，并且所述第一应变Si区具有与所述第二应变Si区相同或不同的晶体取向。第一应变Si区域的应变水平与第二应变Si区域的应变水平不同。

38. 发明授权

US06989058B2 Use of thin SOI to inhibit relaxation of SiGe layers 有权
标题翻译：使用薄SOI抑制SiGe层的弛豫
公开(公告)号：US06989058B2
公开(公告)日：2006-01-24
申请号：US10654232
申请日：2003-09-03
申请人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Huajie Chen , Keith E. Fogel , Devendra K. Sadana
IPC分类号： C30B25/02
CPC分类号： H01L21/7624 , C30B29/52 , C30B31/02 , H01L21/02381 , H01L21/02532 , H01L21/02694 , Y10T428/24917
摘要： High-quality, metastable SiGe alloys are formed on SOI substrates having an SOI layer of about 500 Å or less, the SiGe layers can remain substantially fully strained compared to identical SiGe layers formed on thicker SOI substrates and subsequently annealed and/or oxidized at high temperatures. The present invention thus provides a method of ‘frustrating’ metastable strained SiGe layers by growing them on thin, clean and high-quality SOI substrates.
摘要翻译：在具有大约等于或小于等于或等于SOI层的SOI层的SOI衬底上形成高质量的亚稳态SiGe合金，与形成在较厚SOI衬底上的相同SiGe层相比，SiGe层可以保持基本上完全变形，并随后在高温下退火和/或氧化温度。因此，本发明提供了一种通过在薄的，清洁的和高质量的SOI衬底上生长它们来“挫败”亚稳应变的SiGe层的方法。

39. 发明授权

US06878611B2 Patterned strained silicon for high performance circuits 失效
标题翻译：用于高性能电路的图形应变硅
公开(公告)号：US06878611B2
公开(公告)日：2005-04-12
申请号：US10336147
申请日：2003-01-02
申请人： Devendra K. Sadana , Stephen W. Bedell , Tze-Chiang Chen , Kwang Su Choe , Keith E. Fogel
发明人： Devendra K. Sadana , Stephen W. Bedell , Tze-Chiang Chen , Kwang Su Choe , Keith E. Fogel
IPC分类号： H01L21/76 , H01L21/02 , H01L21/20 , H01L21/324 , H01L21/762 , H01L21/8238 , H01L27/12 , H01L21/36
CPC分类号： H01L21/324 , H01L21/02381 , H01L21/0245 , H01L21/02532 , H01L21/02658 , H01L21/02694 , H01L21/823807 , Y10S438/96
摘要： In the preferred embodiment of this invention a method is described to convert patterned SOI regions into patterned SGOI (silicon-germanium on oxide) by the SiGe/SOI thermal mixing process to further enhance performance of the logic circuit in an embedded DRAM. The SGOI region acts as a template for subsequent Si growth such that the Si is strained, and electron and holes in the Si have higher mobility.
摘要翻译：在本发明的优选实施例中，描述了通过SiGe / SOI热混合工艺将图案化SOI区域转换为图案化SGOI（氧化硅上的硅 - 锗）的方法，以进一步增强嵌入式DRAM中逻辑电路的性能。 SGOI区域用作随后的Si生长的模板，使得Si被应变，并且Si中的电子和空穴具有较高的迁移率。

40. 发明授权

US06841457B2 Use of hydrogen implantation to improve material properties of silicon-germanium-on-insulator material made by thermal diffusion 有权
公开(公告)号：US06841457B2
公开(公告)日：2005-01-11
申请号：US10196611
申请日：2002-07-16
申请人： Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
发明人： Stephen W. Bedell , Keith E. Fogel , Devendra K. Sadana
IPC分类号： H01L29/161 , H01L21/20 , H01L21/265 , H01L21/762 , H01L21/36
CPC分类号： H01L21/76243 , H01L21/02378 , H01L21/02381 , H01L21/02488 , H01L21/02532 , H01L21/02664 , Y10S438/933
摘要： A method of forming a relaxed SiGe-on-insulator substrate having enhanced relaxation, significantly lower defect density and improved surface quality is provided. The method includes forming a SiGe alloy layer on a surface of a first single crystal Si layer. The first single crystal Si layer has an interface with an underlying barrier layer that is resistant to Ge diffusion. Next, ions that are capable of forming defects that allow mechanical decoupling at or near said interface are implanted into the structure and thereafter the structure including the implanted ions is subjected to a heating step which permits interdiffusion of Ge throughout the first single crystal Si layer and the SiGe layer to form a substantially relaxed, single crystal and homogeneous SiGe layer atop the barrier layer. SiGe-on-insulator substrates having the improved properties as well as heterostructures containing the same are also provided.

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