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31. 发明授权

US06912648B2 Stick and spoke replay with selectable delays 失效
标题翻译：棒和语音重播与可选择的延迟
公开(公告)号：US06912648B2
公开(公告)日：2005-06-28
申请号：US10039598
申请日：2001-12-31
申请人： Per Hammarlund , Stephan Jourdan
发明人： Per Hammarlund , Stephan Jourdan
IPC分类号： G06F9/38 , G09F9/30
CPC分类号： G06F9/3861 , G06F9/3842
摘要： A method for stick and spoke replay in a processor. The method of one embodiment comprises dispatching an instruction for execution. The instruction is speculatively executed. It is determined whether the instruction executed correctly. The instruction is routed to a replay mechanism if the instruction did not execute correctly. It is determined incorrect execution of the instruction is due to a long latency operation. The instruction is routed for immediate re-execution if the incorrect execution is not due to the long latency operation. The routing of the instruction for re-execution is delayed if the incorrect execution is due to the long latency operation. The instruction is re-executed if the instruction did not execute correctly. The instruction is retired if the instruction executed correctly.
摘要翻译：一种在处理器中进行棒状和辐条重放的方法。一个实施例的方法包括调度执行指令。该指令被推测执行。确定指令是否正确执行。如果指令执行不正确，指令将被路由到重播机制。确定指令的不正确执行是由于长延迟操作造成的。如果不正确的执行不是由于长延迟操作造成的，则该指令被路由以立即重新执行。如果不正确的执行是由于长延迟操作造成的，则重新执行指令的路由被延迟。如果指令执行不正确，则重新执行指令。如果指令正确执行，指令将退出。

32. 发明申请

US20050071614A1 Method and system for multiple branch paths in a microprocessor 审中-公开
标题翻译：微处理器中多个分支路径的方法和系统
公开(公告)号：US20050071614A1
公开(公告)日：2005-03-31
申请号：US10676310
申请日：2003-09-30
申请人： Stephan Jourdan , Per Hammarlund , Avinash Sodani , James Allen , Francis McKeen , Pierre Michaud
发明人： Stephan Jourdan , Per Hammarlund , Avinash Sodani , James Allen , Francis McKeen , Pierre Michaud
IPC分类号： G06F9/00 , G06F9/318 , G06F9/38
CPC分类号： G06F9/3842 , G06F9/3017 , G06F9/3804 , G06F9/3806 , G06F9/3844 , G06F9/3861
摘要： A method and system for multiple branch paths in a microprocessor is described. The method includes assigning an identification number (ID) to each of a plurality of micro-operations (uops) to identify a branch path to which the uop belongs, determining whether one or more branches are predicted correctly, determining which of the one or more branch paths are dependent on a mispredicted branch, and determining whether one or more of the plurality of uops belong to a branch path that is dependent on a mispredicted branch based on their assigned IDs.
摘要翻译：描述了微处理器中多个分支路径的方法和系统。该方法包括：将识别号码（ID）分配给多个微操作（uop）中的每一个以识别该uop所属的分支路径，确定一个或多个分支是否被正确地预测，确定一个或多个分支路径取决于错误预测的分支，并且基于其分配的ID来确定多个uops中的一个或多个是否属于依赖于错误预测的分支的分支路径。

33. 发明申请

US20050071518A1 Flag value renaming 审中-公开
标题翻译：标志值重命名
公开(公告)号：US20050071518A1
公开(公告)日：2005-03-31
申请号：US10677039
申请日：2003-09-30
申请人： Nicholas Samra , Stephan Jourdan , Jonathan Combs , Avinash Sodani , Per Hammarlund , Michael Cornaby
发明人： Nicholas Samra , Stephan Jourdan , Jonathan Combs , Avinash Sodani , Per Hammarlund , Michael Cornaby
IPC分类号： G06F3/00 , G06F9/30 , G06F9/32 , G06F9/38
CPC分类号： G06F9/30094 , G06F9/3836 , G06F9/3838 , G06F9/384 , G06F9/3857
摘要： According to an embodiment of the invention, a method and apparatus for flag value renaming. An embodiment of a method comprises setting a flag for a processor via a first instruction, the first instruction being either a direct update instruction or an indirect update instruction; if the setting of the flag is by a direct update instruction, executing a succeeding second instruction that reads the flag prior to completion of the first instruction; and if the setting of the flag is by an indirect update instruction, delaying the second instruction until after completion of the first instruction.
摘要翻译：根据本发明的实施例，一种用于标志值重命名的方法和装置。方法的实施例包括经由第一指令设置处理器的标志，第一指令是直接更新指令或间接更新指令; 如果所述标志的设置是通过直接更新指令，则执行在完成所述第一指令之前读取所述标志的后续第二指令; 并且如果所述标志的设置是通过间接更新指令，则延迟所述第二指令直到所述第一指令完成为止。

34. 发明申请

US20050027963A1 System and method for employing a process identifier to minimize aliasing in a linear-addressed cache 失效
标题翻译：用于使用进程标识符来最小化线性寻址高速缓存中的混叠的系统和方法
公开(公告)号：US20050027963A1
公开(公告)日：2005-02-03
申请号：US10917449
申请日：2004-08-13
申请人： Herbert Hum , Stephan Jourdan , Per Hammarlund
发明人： Herbert Hum , Stephan Jourdan , Per Hammarlund
IPC分类号： G06F12/10 , G06F12/08
CPC分类号： G06F12/1054 , G06F12/1063 , G06F12/109
摘要： A system and method for reducing linear address aliasing is described. In one embodiment, a portion of a linear address is combined with a process identifier, e.g., a page directory base pointer to form an adjusted-linear address. The page directory base pointer is unique to a process and combining it with a portion of the linear address produces an adjusted-linear address that provides a high probability of no aliasing. A portion of the adjusted-linear address is used to search an adjusted-linear-addressed cache memory for a data block specified by the linear address. If the data block does not reside in the adjusted-linear-addressed cache memory, then a replacement policy selects one of the cache lines in the adjusted-linear-addressed cache memory and replaces the data block of the selected cache line with a data block located at a physical address produced from translating the linear address. The tag for the cache line selected is a portion of the adjusted linear address and the physical address produced from translating the linear address.
摘要翻译：描述了用于减少线性地址混叠的系统和方法。在一个实施例中，线性地址的一部分与进程标识符（例如，页目录基本指针）组合以形成调整后的线性地址。页面目录基本指针对于进程是唯一的，并且将其与线性地址的一部分组合产生调整的线性地址，其提供没有别名的高概率。调整后的线性地址的一部分用于搜索由线性地址指定的数据块的经调整的线性寻址高速缓冲存储器。如果数据块不在调整后的线性寻址高速缓冲存储器中，则替换策略选择调整后的线性寻址高速缓存存储器中的一条高速缓存行，并用数据块替换所选择的高速缓存线的数据块位于从翻译线性地址产生的物理地址。所选择的高速缓存线的标签是调整后的线性地址的一部分和通过转换线性地址产生的物理地址。

35. 发明授权

US07181597B2 Decoding instructions for trace cache resume state in system passing decoded operations to both trace cache and execution allocation module 失效
标题翻译：解码指令，用于跟踪缓存恢复状态，系统将解码的操作传递到跟踪缓存和执行分配模块
公开(公告)号：US07181597B2
公开(公告)日：2007-02-20
申请号：US11217707
申请日：2005-08-31
申请人： John Alan Miller , Stephan Jourdan
发明人： John Alan Miller , Stephan Jourdan
IPC分类号： G06F9/06
CPC分类号： G06F9/3808 , G06F9/3824 , G06F9/3826
摘要： A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
摘要翻译：管理处理器指令的系统和方法提供增强的性能。该系统和方法提供用解码器将第一指令解码为多个操作。操作的第一个副本从解码器传递到与跟踪缓存相关联的构建引擎。该系统和方法进一步提供将操作的第二副本从解码器直接传递到后端分配模块，使得操作绕过构建引擎并且分配模块处于解码器读取状态。

36. 发明授权

US06950924B2 Passing decoded instructions to both trace cache building engine and allocation module operating in trace cache or decoder reading state 失效
标题翻译：将解码的指令传递到跟踪高速缓存构建引擎和在跟踪缓存或解码器读取状态中操作的分配模块
公开(公告)号：US06950924B2
公开(公告)日：2005-09-27
申请号：US10032565
申请日：2002-01-02
申请人： John Alan Miller , Stephan Jourdan
发明人： John Alan Miller , Stephan Jourdan
IPC分类号： G06F9/00 , G06F9/06 , G06F9/38 , G06F15/00
CPC分类号： G06F9/3808 , G06F9/3824 , G06F9/3826
摘要： A system and method of managing processor instructions provides enhanced performance. The system and method provide for decoding a first instruction into a plurality of operations with a decoder. A first copy of the operations is passed from the decoder to a build engine associated with a trace cache. The system and method further provide for passing a second copy of the operation from the decoder directly to a back end allocation module such that the operations bypass the build engine and the allocation module is in a decoder reading state.
摘要翻译：管理处理器指令的系统和方法提供增强的性能。该系统和方法提供用解码器将第一指令解码为多个操作。操作的第一个副本从解码器传递到与跟踪缓存相关联的构建引擎。该系统和方法进一步提供将操作的第二副本从解码器直接传递到后端分配模块，使得操作绕过构建引擎并且分配模块处于解码器读取状态。

37. 发明授权

US09146745B2 Method and apparatus for partitioned pipelined execution of multiple execution threads 有权
标题翻译：分割流水线执行多个执行线程的方法和装置
公开(公告)号：US09146745B2
公开(公告)日：2015-09-29
申请号：US11479245
申请日：2006-06-29
申请人： Stephan Jourdan , Robert Hinton
发明人： Stephan Jourdan , Robert Hinton
IPC分类号： G06F9/38
CPC分类号： G06F9/3851 , G06F9/3802 , G06F9/3804 , G06F9/3844
摘要： Methods and apparatus for partitioning a microprocessor pipeline to support pipelined branch prediction and instruction fetching of multiple execution threads. A thread selection stage selects a thread from a plurality of execution threads. In one embodiment, storage in a branch prediction output queue is pre-allocated to a portion of the thread in one branch prediction stage in order to prevent stalling of subsequent stages in the branch prediction pipeline. In another embodiment, an instruction fetch stage fetches instructions at a fetch address corresponding to a portion of the selected thread. Another instruction fetch stage stores the instruction data in an instruction fetch output queue if enough storage is available. Otherwise, instruction fetch stages corresponding to the selected thread are invalidated and refetched to avoid stalling preceding stages in the instruction fetch pipeline, which may be fetching instructions of another thread.
摘要翻译：用于分割微处理器流水线以支持流水线分支预测和多个执行线程的指令获取的方法和装置。线程选择阶段从多个执行线程中选择线程。在一个实施例中，分支预测输出队列中的存储被预分配给一个分支预测阶段中的线程的一部分，以便防止分支预测流水线中后续阶段的停顿。在另一个实施例中，指令提取阶段在与所选线程的一部分相对应的获取地址处获取指令。如果有足够的存储可用，另一个指令获取阶段将指令数据存储在指令提取输出队列中。否则，与所选线程相对应的指令获取阶段无效并被重新设计，以避免在指令提取流水线中停止前进阶段，这可能是获取另一线程的指令。

38. 发明授权

US09021279B2 Independent power control of processing cores 有权
公开(公告)号：US09021279B2
公开(公告)日：2015-04-28
申请号：US13087073
申请日：2011-04-14
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.

39. 发明授权

US08103831B2 Efficient method and apparatus for employing a micro-op cache in a processor 有权
标题翻译：在处理器中采用微操作高速缓存的高效方法和装置
公开(公告)号：US08103831B2
公开(公告)日：2012-01-24
申请号：US12060239
申请日：2008-03-31
申请人： Lihu Rappoport , Bob Valentine , Stephan Jourdan , Yoav Almog , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
发明人： Lihu Rappoport , Bob Valentine , Stephan Jourdan , Yoav Almog , Franck Sala , Amir Leibovitz , Ido Ouziel , Ron Gabor
IPC分类号： G06F12/00
CPC分类号： G06F9/3017 , G06F1/3203 , G06F1/3246 , G06F1/3287 , G06F9/30145 , G06F9/3802 , G06F9/382 , Y02D10/171
摘要： Methods and apparatus for using micro-op caches in processors are disclosed. A tag match for an instruction pointer retrieves a set of micro-op cache line access tuples having matching tags. The set is stored in a match queue. Line access tuples from the match queue are used to access cache lines in a micro-op cache data array to supply a micro-op queue. On a micro-op cache miss, a macroinstruction translation engine (MITE) decodes macroinstructions to supply the micro-op queue. Instruction pointers are stored in a miss queue for fetching macroinstructions from the MITE. The MITE may be disabled to conserve power when the miss queue is empty-likewise for the micro-op cache data array when the match queue is empty. Synchronization flags in the last micro-op from the micro-op cache on a subsequent micro-op cache miss indicate where micro-ops from the MITE merge with micro-ops from the micro-op cache.
摘要翻译：公开了在处理器中使用微操作高速缓存的方法和装置。指令指针的标签匹配检索一组具有匹配标签的微操作高速缓存行访问元组。该集合存储在匹配队列中。来自匹配队列的线路访问元组用于访问微操作高速缓存数据阵列中的高速缓存行以提供微操作队列。在微操作缓存未命中时，宏指令转换引擎（MITE）解码宏指令以提供微操作队列。指令指针存储在从MITE获取宏指令的小队列中。当缺席队列为空时，MITE可能会被禁用以节省电力，而当匹配队列为空时，也可以为微操作高速缓存数据阵列。随后微操作高速缓存未命中的微操作高速缓存中的最后一个微操作中的同步标志指示来自MITE的微操作与微操作高速缓存的微操作合并。

40. 发明授权

US08069358B2 Independent power control of processing cores 有权
标题翻译：处理核心的独立功率控制
公开(公告)号：US08069358B2
公开(公告)日：2011-11-29
申请号：US12545657
申请日：2009-08-21
申请人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
发明人： Stephen H. Gunther , Edward A. Burton , Anant Deval , Stephan Jourdan , Robert Greiner , Michael Cornaby
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/324 , G06F1/3287 , G06F1/3296
摘要： Independent power control of two or more processing cores. More particularly, at least one embodiment of the invention pertains to a technique to place at least one processing core in a power state without coordinating with the power state of one or more other processing cores.
摘要翻译：两个或多个处理核心的独立功率控制。更具体地，本发明的至少一个实施例涉及将至少一个处理核放置在功率状态而不与一个或多个其它处理核的功率状态协调的技术。

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