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31. 发明授权

US08968280B2 Dose determination for inducing microcavitation in retinal pigment epithelium (RPE) 有权
标题翻译：用于诱导视网膜色素上皮（RPE）微量化的剂量测定
公开(公告)号：US08968280B2
公开(公告)日：2015-03-03
申请号：US13145605
申请日：2010-01-22
申请人： Charles P. Lin , Clemens Alt , Ho Lee
发明人： Charles P. Lin , Clemens Alt , Ho Lee
IPC分类号： A61B18/18 , A61F9/008
CPC分类号： A61F9/008 , A61F9/00821 , A61F2009/00863
摘要： Methods and systems for controlling selective targeting of retinal pigment epithelium (RPE) cells within a treatment region of the RPE. The methods include (a) depositing a selected amount of energy on a test region of the RPE; (b) determining an extent to which microcavitation has occurred in the test region; and (c) on the basis of the determination, either depositing the selected amount of energy on the treatment region, or depositing an increased amount of energy on the test region, and repeating steps (b) and (c).
摘要翻译：用于控制RPE治疗区域内视网膜色素上皮细胞（RPE）细胞选择性靶向的方法和系统。所述方法包括（a）在RPE的测试区域上沉积选定量的能量; （b）确定在测试区域发生微气蚀的程度; 和（c）基于该确定，将所选择的能量沉积在处理区域上，或者在测试区域上沉积增加的能量，并重复步骤（b）和（c）。

32. 发明授权

US08426916B2 Semiconductor integrated circuit devices having different thickness silicon-germanium layers 有权
标题翻译：具有不同厚度的硅 - 锗层的半导体集成电路器件
公开(公告)号：US08426916B2
公开(公告)日：2013-04-23
申请号：US13476121
申请日：2012-05-21
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/36
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。第二SiGe外延层直接形成在第一SiGe外延层上，以使用不同于第一硅源气体的第二硅源气体来进一步填充源极/漏极沟槽。

33. 发明授权

US08207033B2 Methods of fabricating different thickness silicon-germanium layers on semiconductor integrated circuit devices and semiconductor integrated circuit devices fabricated thereby 有权
标题翻译：在半导体集成电路器件上制造不同厚度的硅 - 锗层的方法和由此制造的半导体集成电路器件
公开(公告)号：US08207033B2
公开(公告)日：2012-06-26
申请号：US12419698
申请日：2009-04-07
申请人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
发明人： Myung-Sun Kim , Hwa-Sung Rhee , Ho Lee , Ji-Hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/02532 , H01L21/0262 , H01L21/02636 , H01L29/165 , H01L29/66636 , H01L29/78
摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.
摘要翻译：提供制造半导体集成电路器件的方法。基板设置有形成在第一和第二区域上的栅极图案。第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

34. 发明授权

US08053131B2 Apparatus and method for determining deterioration of a fuel cell and method for preventing deterioration of the same 有权
标题翻译：用于确定燃料电池劣化的装置和方法及其防止劣化的方法
公开(公告)号：US08053131B2
公开(公告)日：2011-11-08
申请号：US12361221
申请日：2009-01-28
申请人： Ik Jae Son , Byung Ki Ahn , Tae Won Lim , Jong Hyun Lee , Kwon Pil Park , Ho Lee , Chang Won Jung , Seung Chan Oh , Jae Jun Ko , Young Min Kim , Sae Hoon Kim , Jong Jin Yoon , Se Joon Im
发明人： Ik Jae Son , Byung Ki Ahn , Tae Won Lim , Jong Hyun Lee , Kwon Pil Park , Ho Lee , Chang Won Jung , Seung Chan Oh , Jae Jun Ko , Young Min Kim , Sae Hoon Kim , Jong Jin Yoon , Se Joon Im
IPC分类号： H01M8/04
CPC分类号： H01M8/04679 , H01M2/022 , H01M8/0432 , H01M8/0444 , H01M8/045 , H01M8/04507 , H01M8/04552 , H01M8/04701 , H01M8/04835 , H01M2008/1095 , Y10T436/193333
摘要： The present invention provides an apparatus and method for determining deterioration of a fuel cell, the method including measuring in real time fluoride ion concentration or pH value of outflow water from a fuel cell stack during operation in a fuel cell vehicle, calculating a fluoride emission rate from the measured value and, if the calculated fluoride emission rate is out of a predetermined normal range, determining deterioration of an electrolyte membrane of the fuel cell stack.
摘要翻译：本发明提供了一种用于确定燃料电池劣化的装置和方法，该方法包括在燃料电池车辆操作期间实时测量来自燃料电池堆的流出水的氟离子浓度或pH值，计算氟化物排放率并且如果计算出的氟化物排放率超出预定的正常范围，则确定燃料电池堆的电解质膜的劣化。

35. 发明授权

US07981750B2 Methods of fabrication of channel-stressed semiconductor devices 有权
标题翻译：通道应力半导体器件的制造方法
公开(公告)号：US07981750B2
公开(公告)日：2011-07-19
申请号：US12138502
申请日：2008-06-13
申请人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
发明人： Hion-suck Baik , Jong-bong Park , Jung-yun Won , Hwa-sung Rhee , Byung-seo Kim , Ho Lee , Myung-sun Kim , Ji-hye Yi
IPC分类号： H01L21/336
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/165 , H01L29/665 , H01L29/66628 , H01L29/66636 , H01L29/7843 , H01L29/7848 , Y10S438/938
摘要： In one aspect, a method of fabricating a semiconductor device is provided. The method includes forming at least one capping layer over epitaxial source/drain regions of a PMOS device, forming a stress memorization (SM) layer over the PMOS device including the at least one capping layer and over an adjacent NMOS device, and treating the SM layer formed over the NMOS and PMOS devices to induce tensile stress in a channel region of the NMOS device.
摘要翻译：一方面，提供一种制造半导体器件的方法。该方法包括在PMOS器件的外延源极/漏极区域上形成至少一个覆盖层，在包括至少一个覆盖层并且在相邻的NMOS器件上的PMOS器件上形成应力记忆（SM）层，以及处理SM 形成在NMOS和PMOS器件上的层，以在NMOS器件的沟道区域中引起拉伸应力。

36. 发明授权

US07952147B2 Semiconductor device having analog transistor with improved operating and flicker noise characteristics and method of making same 有权
标题翻译：具有具有改善的操作和闪烁噪声特性的模拟晶体管的半导体器件及其制造方法
公开(公告)号：US07952147B2
公开(公告)日：2011-05-31
申请号：US11802281
申请日：2007-05-22
申请人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-sung Rhee , Ho Lee
IPC分类号： H01L21/70
CPC分类号： H01L27/092 , H01L21/823807 , H01L21/823814 , H01L29/4933 , H01L29/665 , H01L29/7843 , H01L29/7848
摘要： A semiconductor device with improved transistor operating and flicker noise characteristics includes a substrate, an analog NMOS transistor and a compressively-strained-channel analog PMOS transistor disposed on the substrate. The device also includes a first etch stop liner (ESL) and a second ESL which respectively cover the NMOS transistor and the PMOS transistor. The relative measurement of flicker noise power of the NMOS and PMOS transistors to flicker noise power of reference unstrained-channel analog NMOS and PMOS transistors at a frequency of 500 Hz is less than 1.
摘要翻译：具有改善的晶体管操作和闪烁噪声特性的半导体器件包括衬底，模拟NMOS晶体管和设置在衬底上的压缩应变通道模拟PMOS晶体管。该器件还包括分别覆盖NMOS晶体管和PMOS晶体管的第一蚀刻停止衬垫（ESL）和第二ESL。在500 Hz频率下，NMOS和PMOS晶体管的闪烁噪声功率相对于参考无约束通道模拟NMOS和PMOS晶体管的闪烁噪声功率的相对测量值小于1。

37. 发明授权

US07714394B2 CMOS semiconductor devices having elevated source and drain regions and methods of fabricating the same 有权
标题翻译：具有升高的源极和漏极区域的CMOS半导体器件及其制造方法
公开(公告)号：US07714394B2
公开(公告)日：2010-05-11
申请号：US11285978
申请日：2005-11-23
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L23/58
CPC分类号： H01L29/7834 , H01L21/265 , H01L21/823807 , H01L21/823814 , H01L29/665 , H01L29/6653 , H01L29/6656 , H01L29/66628
摘要： A Complementary Metal Oxide Semiconductor (CMOS) device is provided. The CMOS device includes an isolation layer provided in a semiconductor substrate to define first and second active regions. First and second gate patterns are disposed to cross over the first and second active regions, respectively. A first elevated source region and a first elevated drain region are disposed at both sides of the first gate pattern respectively, and a second elevated source region and a second elevated drain region are disposed at both sides of the second gate pattern respectively. The first elevated source/drain regions are provided on the first active region, and the second elevated source/drain regions are provided on the second active region. A first gate spacer is provided between the first gate pattern and the first elevated source/drain regions. A second gate spacer is provided to cover edges of the second elevated source/drain regions adjacent to the second gate pattern and an upper sidewall of the second gate pattern. Methods of fabricating the CMOS device is also provided.
摘要翻译：提供互补金属氧化物半导体（CMOS）器件。 CMOS器件包括设置在半导体衬底中以限定第一和第二有源区的隔离层。第一和第二栅极图案分别设置成跨越第一和第二有源区域。第一升高的源极区域和第一升高的漏极区域分别设置在第一栅极图案的两侧，并且第二升高的源极区域和第二升高的漏极区域分别设置在第二栅极图案的两侧。第一升高的源极/漏极区域设置在第一有源区上，而第二升高的源极/漏极区域设置在第二有源区域上。在第一栅极图案和第一升高的源极/漏极区域之间提供第一栅极间隔物。设置第二栅极间隔物以覆盖与第二栅极图案相邻的第二升高的源极/漏极区域和第二栅极图案的上侧壁的边缘。还提供了制造CMOS器件的方法。

38. 发明授权

US07611951B2 Method of fabricating MOS transistor having epitaxial region 有权
标题翻译：制造具有外延区域的MOS晶体管的方法
公开(公告)号：US07611951B2
公开(公告)日：2009-11-03
申请号：US11517246
申请日：2006-09-08
申请人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
发明人： Tetsuji Ueno , Hwa-Sung Rhee , Ho Lee
IPC分类号： H01L21/336
CPC分类号： H01L29/7848 , H01L21/26506 , H01L21/26513 , H01L21/2658 , H01L29/1083 , H01L29/165 , H01L29/6653 , H01L29/6656 , H01L29/66636
摘要： Example embodiments relate to a method of manufacturing a semiconductor device. Other example embodiments relate to a method of manufacturing a metal-oxide-semiconductor (MOS) transistor having an epitaxial region disposed in a lower portion of sidewalls of a gate pattern. Provided is a method of manufacturing a MOS transistor having an epitaxial region which improves an epitaxial growth rate and which may have fewer defects. The method of manufacturing a MOS transistor having an epitaxial region may include forming a gate pattern on a semiconductor substrate, forming a first ion implantation region having a first damage profile by implanting first impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask, forming a second ion implantation region having a second damage profile adjacent to the first damage profile by implanting second impurity ions into the semiconductor substrate using the gate pattern as an ion implantation mask and partially etching a lower portion of sidewalls of the gate pattern and forming in-situ an epitaxial region on the etched semiconductor substrate.
摘要翻译：示例实施例涉及制造半导体器件的方法。其他示例实施例涉及制造具有设置在栅极图案的侧壁的下部中的外延区域的金属氧化物半导体（MOS）晶体管的方法。提供一种制造具有提高外延生长速率并且可能具有较少缺陷的外延区域的MOS晶体管的方法。制造具有外延区域的MOS晶体管的方法可以包括在半导体衬底上形成栅极图案，通过使用栅极图案作为离子注入，将第一杂质离子注入到半导体衬底中，形成具有第一损伤分布的第一离子注入区域通过使用所述栅极图案作为离子注入掩模将所述第二杂质离子注入到所述半导体衬底中，形成具有与所述第一损伤分布相邻的第二损伤分布的第二离子注入区，并部分地蚀刻所述栅极图案的侧壁的下部;以及在蚀刻的半导体衬底上原位形成外延区域。

39. 发明申请

US20080191244A1 METHODS OF FABRICATING INTEGRATED CIRCUIT DEVICES INCLUDING STRAINED CHANNEL REGIONS AND RELATED DEVICES 审中-公开
标题翻译：制作集成电路设备的方法，包括应变通道区域和相关设备
公开(公告)号：US20080191244A1
公开(公告)日：2008-08-14
申请号：US11862452
申请日：2007-09-27
申请人： Ki chul Kim , Ho Lee , Jung-deog Lee
发明人： Ki chul Kim , Ho Lee , Jung-deog Lee
IPC分类号： H01L27/092 , H01L21/8238 , H01L29/778
CPC分类号： H01L21/823807 , H01L21/823814 , H01L29/0653 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/7848
摘要： A method of fabricating an integrated circuit device includes forming first and second gate patterns on surfaces of a semiconductor substrate in PMOS and NMOS regions, respectively, of the substrate. P-type source/drain regions are epitaxially grown on opposite sides of the first gate pattern in the PMOS region to exert compressive stress on a first channel region therebetween adjacent the first gate pattern. N-type source/drain regions are epitaxially grown on opposite sides of the second gate pattern in the NMOS region to exert tensile stress on a second channel region therebetween adjacent the second gate pattern. Related devices are also discussed.
摘要翻译：一种制造集成电路器件的方法包括分别在衬底的PMOS和NMOS区域中的半导体衬底的表面上形成第一和第二栅极图案。 P型源极/漏极区域在PMOS区域中的第一栅极图案的相对侧上外延生长，以在邻近第一栅极图案的第一沟道区域上施加压应力。 N型源极/漏极区域在NMOS区域中的第二栅极图案的相对侧上外延生长，以在邻近第二栅极图案的第二沟道区域上施加拉伸应力。还讨论了相关设备。

40. 发明授权

US07361563B2 Methods of fabricating a semiconductor device using a selective epitaxial growth technique 有权
标题翻译：使用选择性外延生长技术制造半导体器件的方法
公开(公告)号：US07361563B2
公开(公告)日：2008-04-22
申请号：US11299447
申请日：2005-12-09
申请人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
发明人： Dong-Suk Shin , Hwa-Sung Rhee , Tetsuji Ueno , Ho Lee , Seung-Hwan Lee
IPC分类号： H01L21/205 , H01L29/80 , H01L21/336
CPC分类号： H01L29/7848 , H01L29/165 , H01L29/6656 , H01L29/6659 , H01L29/66628 , H01L29/66636 , H01L29/7834
摘要： Methods of fabricating a semiconductor device using a selective epitaxial growth technique include forming a recess in a semiconductor substrate. The substrate having the recess is loaded into a reaction chamber. A semiconductor source gas and a main etching gas are injected into the reaction chamber to selectively grow an epitaxial semiconductor layer on a sidewall and on a bottom surface of the recess. A selective etching gas is injected into the reaction chamber to selectively etch a fence of the epitaxial semiconductor layer which is adjacent to the sidewall of the recess and grown to a level that is higher than an upper surface of the semiconductor substrate.
摘要翻译：使用选择性外延生长技术制造半导体器件的方法包括在半导体衬底中形成凹部。将具有凹部的基板装入反应室。将半导体源气体和主蚀刻气体注入到反应室中，以选择性地在凹槽的侧壁和底表面上生长外延半导体层。选择性蚀刻气体被注入到反应室中，以选择性地蚀刻外延半导体层的与凹槽的侧壁相邻的栅栏，并生长到高于半导体衬底的上表面的水平。

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