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31. 发明授权

US06704861B1 Mechanism for executing computer instructions in parallel 失效
标题翻译：并行执行计算机指令的机制
公开(公告)号：US06704861B1
公开(公告)日：2004-03-09
申请号：US08752729
申请日：1996-11-19
申请人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
发明人： Francis X. McKeen , Michael C. Adler , Joel S. Emer , Robert P. Nix , David J. Sager , P. Geoffrey Lowney
IPC分类号： G06F938
CPC分类号： G06F9/3842 , G06F9/3851 , G06F9/3865
摘要： A mechanism for executing computer instructions in parallel includes a compiler for generating and grouping instructions into a plurality of sets of instructions to be executed in parallel, each set having a unique identification. A computer system having a real state and a speculative state executes the sets in parallel, the computer system executing a particular set of instructions in the speculative state if the instructions of the particular set have dependencies which can not be resolved until the instructions are actually executed. The computer system generates speculative data while executing instructions in the speculative state. Logic circuits are provided to detect any exception conditions which occur while executing the particular set in the speculative state. If the particular set is subject to an exception condition, the instructions of the set are re-executed to resolve the exception condition, and to incorporate the speculative data in the real state of the computer system.
摘要翻译：用于并行执行计算机指令的机构包括：编译器，用于将指令生成和分组成并行执行的多组指令，每组具有唯一的标识。具有实际状态和推测状态的计算机系统并行地执行集合，如果特定集合的指令具有在实际执行指令之前无法解析的依赖关系，则计算机系统在推测状态下执行特定指令集。计算机系统在推测状态下执行指令时生成推测数据。提供逻辑电路以检测在推测状态下执行特定集合时发生的任何异常情况。如果特定集合受到异常条件的影响，则重新执行该集合的指令以解决异常条件，并将推测数据并入计算机系统的实际状态。

32. 发明授权

US06675192B2 Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers 有权
标题翻译：临时停止线程执行，直到在工作寄存器中识别的内存位置监视武装事件
公开(公告)号：US06675192B2
公开(公告)日：2004-01-06
申请号：US10293975
申请日：2002-11-11
申请人： Joel S. Emer , Rebecca L. Stamm , Bruce E. Edwards , Matthew H. Reilly , Craig B. Zilles , Tryggve Fossum , Christopher F. Joerg , James E. Hicks, Jr.
发明人： Joel S. Emer , Rebecca L. Stamm , Bruce E. Edwards , Matthew H. Reilly , Craig B. Zilles , Tryggve Fossum , Christopher F. Joerg , James E. Hicks, Jr.
IPC分类号： G06F948
CPC分类号： G06F9/30087 , G06F9/3009 , G06F9/3851 , G06F9/485 , G06F9/526 , Y02D10/24
摘要： Execution of a program's instructions in a simultaneous multithreaded processor is halted while the program is waiting for one or more events to occur by first arming an event monitor upon an arm instruction, that is, identifying to the event monitor one or more events to be monitored, such as a modification to a value or state of an identified memory location or group of locations, and setting a watch flag to indicate enable the event monitor. Upon execution of a quiesce request instruction, the program quiesces if the watch flag is set, and a timer is started. Upon observation by the event monitor of an identified event, or upon expiration of the timer, the watch flag is cleared and execution of the program resumes.
摘要翻译：当程序正在等待一个或多个事件发生时，程序在同步多线程处理器中的指令的执行是通过在手臂指令上首先布防事件监视器来进行的，也就是识别事件监视器要监视的一个或多个事件，例如对所识别的存储器位置或一组位置的值或状态的修改，以及设置监视标志以指示启用事件监视器。在执行静默请求指令时，如果设置了监视标志，并且启动了定时器，则该程序静止。在通过事件监视器对所识别的事件进行观察时，或者在定时器到期时，清除监视标志并重新执行程序。

33. 发明授权

US5933860A Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted 失效
标题翻译：多指针指令缓存，具有基于指令的探针提示生成和训练，从而预测缓存库或接下来要访问的方式
公开(公告)号：US5933860A
公开(公告)日：1999-08-03
申请号：US902487
申请日：1997-07-29
申请人： Joel S. Emer , Simon Steely , Edward J. McLellan
发明人： Joel S. Emer , Simon Steely , Edward J. McLellan
IPC分类号： G06F9/38 , G06F12/08 , G06F9/34 , G06F12/06
CPC分类号： G06F9/3806 , G06F12/0862 , G06F9/3824 , G06F9/3832 , G06F2212/6082
摘要： A computer system including an instruction cache (I-cache) having a plurality of banks for storing a subset of data from memory is shown to include a prediction mechanism for predicting which bank of the I-cache contains the required data. A prediction value, including a sequential prediction hint and a branch prediction hint, is associated with each instruction stored in the I-cache. The prediction value may either be stored with the I-cache data, or in a separate memory included before the I-cache. If the predicted value is incorrect, the predicted hint is `trained` to provide a higher degree of accuracy for repetitive instruction stream operation. Processor performance is additionally improved by providing a branch hint that allows for smoother transition between changing instruction streams.
摘要翻译：包括具有用于存储来自存储器的数据子集的多个存储体的指令高速缓存（I缓存）的计算机系统被示为包括用于预测I缓存的哪个存储体包含所需数据的预测机制。包括顺序预测提示和分支预测提示的预测值与存储在I缓存中的每个指令相关联。可以将预测值与I缓存数据一起存储，或者存储在I缓存之前的单独的存储器中。如果预测值不正确，则预测提示被“训练”，以为重复的指令流操作提供更高的准确度。通过提供一个分支提示，可以更改处理器性能，从而在更改指令流之间实现更平滑的转换。

34. 发明授权

US07555703B2 Method and apparatus for reducing false error detection in a microprocessor 有权
标题翻译：用于减少微处理器中的错误检测的方法和装置
公开(公告)号：US07555703B2
公开(公告)日：2009-06-30
申请号：US10871430
申请日：2004-06-17
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors. A pi bit is propagated with an instruction through an instruction flow path. When a parity error is detected, the pi bit is set, instead of raising a machine check exception. Upon reaching a commit point, the processor can determine if the instruction was on a wrong path.
摘要翻译：减少微处理器中的错误检测的技术。通过指令流程路径，通过指令传播pi位。当检测到奇偶校验错误时，设置pi位，而不是提高机器检查异常。达到提交点后，处理器可以确定指令是否在错误的路径上。

35. 发明授权

US07543221B2 Method and apparatus for reducing false error detection in a redundant multi-threaded system 有权
标题翻译：用于减少冗余多线程系统中的错误检测的方法和装置
公开(公告)号：US07543221B2
公开(公告)日：2009-06-02
申请号：US10948813
申请日：2004-09-22
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver , Michael J. Smith
IPC分类号： G06F11/00
CPC分类号： G06F9/3865 , G06F11/10
摘要： A technique to reduce false error detection in microprocessors within a redundant multi-threaded computing environment. A pi bit is propagated with at least two instructions through an instruction flow path. Results of executing the instruction are compared to see if an error has occurred and if so, the pi bits are examined to determine which instruction contains the error.
摘要翻译：一种在冗余多线程计算环境中减少微处理器中的错误检测的技术。通过指令流程路径，使用至少两个指令来传播pi位。比较执行指令的结果，看是否发生错误，如果是，则检查pi位，以确定哪个指令包含错误。

36. 发明授权

US07475321B2 Detecting errors in directory entries 有权
标题翻译：检测目录条目中的错误
公开(公告)号：US07475321B2
公开(公告)日：2009-01-06
申请号：US11027391
申请日：2004-12-29
申请人： Sudhanva Gurumurthi , Arijit Biswas , Joel S. Emer , Shubhendu S. Mukherjee
发明人： Sudhanva Gurumurthi , Arijit Biswas , Joel S. Emer , Shubhendu S. Mukherjee
IPC分类号： G06F11/00 , G06F11/30 , G08C25/00 , H03M13/00 , H04L1/00
CPC分类号： G06F11/0793 , G06F11/0724 , G06F12/0817 , G06F2212/1032 , Y10S707/99933 , Y10S707/99934
摘要： In one embodiment, the present invention includes a system, which may be a multiprocessor system having multiple nodes, each with a processor and a cache. The system may include a directory stored in a memory that includes entries having coherency information. At least one of the nodes may be configured to detect an error in an entry of the directory based on a coherency protocol and a state of a status indicator and presence vector of the entry, and without the storage of error correction or parity information in the entry. In some embodiments, the node may correct the error using state information obtained from other nodes.
摘要翻译：在一个实施例中，本发明包括一种系统，其可以是具有多个节点的多处理器系统，每个具有处理器和高速缓存。系统可以包括存储在包括具有一致性信息的条目的存储器中的目录。节点中的至少一个可以被配置为基于一致性协议和条目的状态指示符和存在向量的状态来检测目录的条目中的错误，并且在不存在错误校正或奇偶校验信息的存储中条目。在一些实施例中，节点可以使用从其他节点获得的状态信息来校正错误。

37. 发明授权

US07404070B1 Branch prediction combining static and dynamic prediction techniques 失效
标题翻译：分支预测结合静态和动态预测技术
公开(公告)号：US07404070B1
公开(公告)日：2008-07-22
申请号：US09723687
申请日：2000-11-28
申请人： Harish G. Patil , Joel S. Emer , Stephen Felix
发明人： Harish G. Patil , Joel S. Emer , Stephen Felix
IPC分类号： G06F9/00
CPC分类号： G06F9/382 , G06F9/3005 , G06F9/3846 , G06F9/3848
摘要： A computer system comprises a processor that comprises a hardware branch predictor and software instructions executed by the processor. The software instructions comprise conditional branch instructions and separate static branch prediction instructions. The static branch prediction instructions comprise a plurality of groups of static branch prediction bits, each group being configurable to provide prediction information for a separate conditional branch instruction.
摘要翻译：计算机系统包括处理器，其包括由处理器执行的硬件分支预测器和软件指令。软件指令包括条件分支指令和单独的静态分支预测指令。静态分支预测指令包括多组静态分支预测比特，每组可配置为单独的条件分支指令提供预测信息。

38. 发明授权

US07386756B2 Reducing false error detection in a microprocessor by tracking instructions neutral to errors 有权
标题翻译：通过跟踪中性到错误的指令，减少微处理器中的错误检测
公开(公告)号：US07386756B2
公开(公告)日：2008-06-10
申请号：US10871429
申请日：2004-06-17
申请人： Joel S. Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt , Christopher T. Weaver
发明人： Joel S. Emer , Shubhendu S. Mukherjee , Steven K. Reinhardt , Christopher T. Weaver
IPC分类号： G06F11/00 , G06F11/10
CPC分类号： G06F11/0721 , G06F9/30145 , G06F9/30181 , G06F9/3865 , G06F11/0751 , G06F11/1052 , G06F11/1407
摘要： A technique to reduce false error detection in microprocessors by tracking instructions neutral to errors. As an instruction is decoded, an anti-pi bit is tagged to the decoded instruction. When a parity error is detected, an instruction queue first checks if the anti-pi bit is set. If the anti-pi bit is set, then instruction is neutral to errors, and the pi bit need not be set. Prefetch, branch predict hint and NOP are types of instructions that are neutral to errors.
摘要翻译：通过跟踪中性到错误的指令来减少微处理器中的错误检测的技术。当指令被解码时，反码比特被标记到解码指令。当检测到奇偶校验错误时，指令队列首先检查反pi位是否被设置。如果反pi位被置位，则指令对于错误是中性的，并且不需要设置pi位。预取，分支预测提示和NOP是对错误中立的指令类型。

39. 发明授权

US07353365B2 Implementing check instructions in each thread within a redundant multithreading environments 有权
标题翻译：在冗余多线程环境中的每个线程中实现检查指令
公开(公告)号：US07353365B2
公开(公告)日：2008-04-01
申请号：US10953887
申请日：2004-09-29
申请人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver
发明人： Shubhendu S. Mukherjee , Joel S. Emer , Steven K. Reinhardt , Christopher T. Weaver
IPC分类号： G06F9/318
CPC分类号： G06F11/1494 , G06F11/1695
摘要： A method and apparatus for a checker instruction in a redundant multithreading environment is described. In one embodiment, when RMT requires, a processor may issue a checker instruction in both a leading thread and a trailing thread. The checker instruction may travel down individual pipelines for each thread independently until it reaches a buffer at the end of each pipeline. Then, prior to committing the checker instruction, the checker instruction looks for its counterpart and does a comparison of the instructions. If the checker instructions match, the checker instructions commit and retires otherwise an error is declared.
摘要翻译：描述用于冗余多线程环境中的检查指令的方法和装置。在一个实施例中，当RMT需要时，处理器可以在前导线程和后退线程中发出校验指令。检查器指令可以独立地沿着每个线程的各个管道下行，直到它到达每个管道末端的缓冲区。然后，在提交检查指令之前，检验员指令寻找其对应方，并对指令进行比较。如果检查器指令匹配，则检查器指令提交并退出，否则声明错误。

40. 发明授权

US07343602B2 Software controlled pre-execution in a multithreaded processor 有权
标题翻译：软件控制在多线程处理器中的预执行
公开(公告)号：US07343602B2
公开(公告)日：2008-03-11
申请号：US10029699
申请日：2001-12-18
申请人： Chi-Keung Luk , Joel S. Emer
发明人： Chi-Keung Luk , Joel S. Emer
IPC分类号： G06F9/46 , G06F9/44 , G06F12/00
CPC分类号： G06F9/4843 , G06F8/4442 , G06F9/383 , G06F9/3834 , G06F9/3842 , G06F9/3851 , G06F9/3861 , G06F11/141 , G06F11/1497
摘要： A processor capable of running multiple threads runs a program in one thread (called the “main” thread) and at least a portion of the same program in another thread (called the “pre-execution” thread). The program in the main thread includes instructions that cause the processor to start and stop pre-execution threads and direct the processor as to which part of the program is to be run through the pre-execution threads. Preferably, such instructions cause the pre-execution thread to run ahead of the main thread in program order. In that way, any cache miss conditions that are encountered by the pre-execution thread are resolved before the main thread requires that same data. Therefore, the main thread should encounter few or no cache miss conditions.
摘要翻译：能够运行多个线程的处理器在一个线程（称为“主”线程）中运行程序，并在另一个线程（称为“预执行”线程）中运行相同程序的至少一部分。主线程中的程序包括使处理器启动和停止预执行线程并将处理器指示为通过预执行线程运行程序的哪些部分的指令。优选地，这样的指令使得预执行线程以程序顺序在主线程之前运行。以这种方式，预执行线程遇到的任何高速缓存未命中情况都在主线程需要相同数据之前解决。因此，主线程应该遇到很少或没有缓存未命中的条件。

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