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31. 发明授权

US06541320B2 Method to controllably form notched polysilicon gate structures 失效
标题翻译：可控地形成切口多晶硅栅极结构的方法
公开(公告)号：US06541320B2
公开(公告)日：2003-04-01
申请号：US09928210
申请日：2001-08-10
申请人： Jeffrey Brown , Richard Wise , Hongwen Yan , Qingyun Yang , Chienfan Yu
发明人： Jeffrey Brown , Richard Wise , Hongwen Yan , Qingyun Yang , Chienfan Yu
IPC分类号： H01L21336
CPC分类号： H01L21/32137 , H01L21/28114 , H01L21/32139 , H01L21/82385 , H01L29/42376
摘要： A method and structure for forming a notched gate structure having a gate conductor layer on a gate dielectric layer. The gate conductor layer has a first thickness. The inventive method includes patterning a mask over the gate conductor layer, etching the gate conductor layer in regions not protected by the mask to a reduced thickness, (the reduced thickness being less than the first thickness), depositing a passivating film over the gate conductor layer, etching the passivating film to remove the passivating film from horizontal portions of the gate conductor layer (using an anisotropic etch), selectively etching the gate conductor layer to remove the gate conductor layer from all regions not protected by the mask or the passivating film. This forms undercut notches within the gate conductor layer at corner locations where the gate conductor meets the gate dielectric layer. The passivating film comprises a C-containing film, a Si-containing film, a Si—C-containing film or combinations thereof.
摘要翻译：一种用于形成在栅极介电层上具有栅极导体层的缺口栅极结构的方法和结构。栅极导体层具有第一厚度。本发明的方法包括在栅极导体层上图案化掩模，在未被掩模保护的区域中将栅极导体层蚀刻到减小的厚度（减小的厚度小于第一厚度），在栅极导体上沉积钝化膜蚀刻钝化膜以从栅极导体层的水平部分去除钝化膜（使用各向异性蚀刻），选择性地蚀刻栅极导体层以从不受掩模或钝化膜保护的所有区域去除栅极导体层。这在栅极导体与栅极介电层相遇的拐角处形成栅极导体层内的底切凹口。钝化膜包括含C的膜，含Si膜，含Si-C的膜或其组合。

32. 发明申请

US20130295773A1 Method for Simultaneously Forming Features of Different Depths in a Semiconductor Substrate 有权
标题翻译：同时形成半导体基板中不同深度特征的方法
公开(公告)号：US20130295773A1
公开(公告)日：2013-11-07
申请号：US13865223
申请日：2013-04-18
申请人： Habib Hichri , Xi Li , Richard Wise
发明人： Habib Hichri , Xi Li , Richard Wise
IPC分类号： H01L21/3065
CPC分类号： H01L21/3065 , H01L21/76229 , H01L21/84 , H01L27/1087 , H01L29/66181
摘要： Embodiments of the invention may include first providing a stack of layers including a semiconductor substrate, a buried oxide layer on the semiconductor substrate, a semiconductor-on-insulator layer on the buried-oxide layer, a nitride layer on the semiconductor-on-insulator layer, and a silicon oxide layer on the nitride layer. A first opening and second opening with a smaller cross-sectional area than the first opening are then formed in the silicon oxide layer, the nitride layer, the semiconductor-on-insulator layer, and the buried-oxide layer. The first opening and the second opening are then etched with a first etching gas. The first opening and the second opening are then etched with a second etching gas, which includes the first etching gas and a halogenated silicon compound, for example, silicon tetrafluoride or silicon tetrachloride. In one embodiment, the first etching gas includes hydrogen bromide, nitrogen trifluoride, and oxygen.
摘要翻译：本发明的实施例可以包括首先提供包括半导体衬底，半导体衬底上的掩埋氧化物层，掩埋氧化物层上的绝缘体上半导体层，绝缘体上半导体上的氮化物层层和氮化物层上的氧化硅层。然后在氧化硅层，氮化物层，绝缘体上半导体层和掩埋氧化物层上形成具有比第一开口更小的横截面面积的第一开口和第二开口。然后用第一蚀刻气体蚀刻第一开口和第二开口。然后用第二蚀刻气体蚀刻第一开口和第二开口，第二蚀刻气体包括第一蚀刻气体和卤化硅化合物，例如四氟化硅或四氯化硅。在一个实施方案中，第一蚀刻气体包括溴化氢，三氟化氮和氧。

33. 发明申请

US20120190189A1 Three Dimensional Integration and Methods of Through Silicon Via Creation 失效
标题翻译：通过创建硅通过三维集成和方法
公开(公告)号：US20120190189A1
公开(公告)日：2012-07-26
申请号：US13422415
申请日：2012-03-16
申请人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
发明人： Mukta G. Farooq , Emily R. Kinser , Richard Wise , Hakeem Yusuff
IPC分类号： H01L21/768
CPC分类号： H01L21/76847 , H01L21/0337 , H01L21/32136 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2225/06541 , H01L2924/0002 , H01L2924/12044 , H01L2924/00
摘要： A method includes patterning a photoresist layer on a structure to define an opening and expose a first planar area on a sacrificial substrate layer, etching to the exposed first planar area to form a cavity having a first depth in the structure, removing a portion of the photoresist to increase the size of the opening to define a second planar area on the sacrificial substrate layer, forming a doped portion in the sacrificial substrate layer, and etching the cavity to increase the depth of the cavity to expose a first conductor in the structure and to increase the planar area and depth of a portion of the cavity to expose a second conductor in the structure.
摘要翻译：一种方法包括在结构上图案化光致抗蚀剂层以限定开口并暴露牺牲衬底层上的第一平面区域，蚀刻到暴露的第一平面区域以形成具有在结构中的第一深度的空腔，光致抗蚀剂以增加开口的尺寸以在牺牲衬底层上限定第二平面区域，在牺牲衬底层中形成掺杂部分，以及蚀刻空腔以增加空腔的深度以暴露结构中的第一导体，以及以增加空腔的一部分的平面面积和深度以暴露结构中的第二导体。

34. 发明授权

US07919379B2 Dielectric spacer removal 有权
标题翻译：介质垫片去除
公开(公告)号：US07919379B2
公开(公告)日：2011-04-05
申请号：US11852906
申请日：2007-09-10
申请人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
发明人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
IPC分类号： H01L21/00 , H01L21/336
CPC分类号： H01L21/31116 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

35. 发明申请

US20090189242A1 METHOD FOR NON-SELECTIVE SHALLOW TRENCH ISOLATION REACTIVE ION ETCH FOR PATTERNING HYBRID-ORIENTED DEVICES COMPATIBLE WITH HIGH-PERFORMANCE HIGHLY-INTEGRATED LOGIC DEVICES 失效
标题翻译：用于非选择性低温分离隔离反应离子蚀刻的方法，适用于兼容高性能高度集成逻辑器件的混合器件
公开(公告)号：US20090189242A1
公开(公告)日：2009-07-30
申请号：US12020887
申请日：2008-01-28
申请人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
发明人： Gregory Costrini , David M. Dobuzinsky , Thomas S. Kanarsky , Munir D. Naeem , Christopher D. Sheraw , Richard Wise
IPC分类号： H01L29/00 , H01L21/762
CPC分类号： H01L29/045 , H01L21/76224
摘要： Disclosed are embodiments of a hybrid-orientation technology (HOT) wafer and a method of forming the HOT wafer with improved shallow trench isolation (STI) structures for patterning devices in both silicon-on-insulator (SOI) regions, having a first crystallographic orientation, and bulk regions, having a second crystallographic orientation. The improved STI structures are formed using a non-selective etch process to ensure that all of the STI structures and, particularly, the STI structures at the SOI-bulk interfaces, each extend to the semiconductor substrate and have an essentially homogeneous (i.e., single material) and planar (i.e., divot-free) bottom surface that is approximately parallel to the top surface of the substrate. Optionally, an additional selective etch process can be used to extend the STI structures a predetermined depth into the substrate.
摘要翻译：公开了混合取向技术（HOT）晶片的实施例以及形成具有改进的浅沟槽隔离（STI）结构的HOT晶片的方法，用于在绝缘体上硅（SOI）区域中图案化器件，具有第一晶体取向和具有第二结晶取向的体区。使用非选择性蚀刻工艺形成改进的STI结构，以确保所有STI结构，特别是SOI-体界面处的STI结构各自延伸到半导体衬底并且具有基本均匀的（即，单个材料）和大致平行于衬底的顶表面的平面（即，无自由）底表面。可选地，可以使用附加的选择性蚀刻工艺来将STI结构延伸到衬底中的预定深度。

36. 发明申请

US20090065817A1 DIELECTRIC SPACER REMOVAL 有权
标题翻译：电介质隔离器
公开(公告)号：US20090065817A1
公开(公告)日：2009-03-12
申请号：US11852906
申请日：2007-09-10
申请人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
发明人： Eduard A. Cartier , Rashmi Jha , Sivananda Kanakasabapathy , Xi Li , Renee T. Mo , Vijay Narayanan , Vamsi Paruchuri , Mark T. Robson , Kathryn T. Schonenberg , Michelle L. Steen , Richard Wise , Ying Zhang
IPC分类号： H01L21/311 , H01L29/78
CPC分类号： H01L21/31116 , H01L29/6653 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： The present invention relates to semiconductor devices, and more particularly to a process and structure for removing a dielectric spacer selective to a surface of a semiconductor substrate with substantially no removal of the semiconductor substrate. The method of the present invention can be integrated into a conventional CMOS processing scheme or into a conventional BiCMOS processing scheme. The method includes forming a field effect transistor on a semiconductor substrate, the FET comprising a dielectric spacer and the gate structure, the dielectric spacer located adjacent a sidewall of the gate structure and over a source/drain region in the semiconductor substrate; depositing a first nitride layer over the FET; and removing the nitride layer and the dielectric spacer selective to the semiconductor substrate with substantially no removal of the semiconductor substrate.
摘要翻译：本发明涉及半导体器件，更具体地说，涉及一种基本上不去除半导体衬底去除对半导体衬底的表面有选择性的介电隔离层的工艺和结构。本发明的方法可以集成到常规的CMOS处理方案中，或者被整合到常规的BiCMOS处理方案中。该方法包括在半导体衬底上形成场效应晶体管，所述FET包括电介质间隔物和所述栅极结构，所述电介质隔离物邻近所述栅极结构的侧壁并位于所述半导体衬底中的源极/漏极区域上; 在所述FET上沉积第一氮化物层; 并且基本上不去除半导体衬底，去除对半导体衬底的选择性的氮化物层和电介质衬垫。

37. 发明申请

US20070216246A1 POWER GENERATING SYSTEMS 失效
公开(公告)号：US20070216246A1
公开(公告)日：2007-09-20
申请号：US11485332
申请日：2006-07-13
申请人： Richard Wise
发明人： Richard Wise
IPC分类号： H02K49/00 , H02K47/00 , H02K16/02
CPC分类号： H02K7/025 , B60K17/12 , H02K49/102 , H02K49/108 , Y02E60/16 , Y02T10/6204
摘要： A power generating system includes a torque converter system receiving a rotational motion having a first torque from a source and producing a rotational output having a second torque different from the first torque, a transfer system having a first portion coupled to the rotational output of the torque converter system and a second portion magnetically coupled to the first portion, and a generator system coupled to the transfer system to produce and electrical output.

38. 发明申请

US20060254960A1 Apparatus and method for isolating materials 审中-公开
公开(公告)号：US20060254960A1
公开(公告)日：2006-11-16
申请号：US11455806
申请日：2006-06-20
申请人： Richard Wise
发明人： Richard Wise
IPC分类号： B03C1/00
CPC分类号： B03C1/04 , B03C1/22 , B03C1/23
摘要： Apparatus is provided for separating non-magnetic mineral values from a source containing magnetic material and non magnetic material. The apparatus includes first and second conveyers in overlying relation which counter-rotate relative to one another. One of the conveyers includes a magnetic assembly which cooperates with paddles on the upper conveyer to progressively isolate values from magnetic material. Multiple stages are provided for intermittent magnetic interactions such that the non-magnetic materials are effectively isolated from the magnetic materials.

39. 发明申请

US20060226725A1 Multivariable generator and method of using the same 失效
标题翻译：多变量发生器及其使用方法
公开(公告)号：US20060226725A1
公开(公告)日：2006-10-12
申请号：US11451499
申请日：2006-06-13
申请人： Richard Wise
发明人： Richard Wise
IPC分类号： H02K21/12 , H02K1/22
CPC分类号： H02K21/24 , H02K21/48
摘要： A generator device for generating electrical energy includes a rotor having a first set of even-numbered of magnetic sources distributed along a first radius of the rotor, and a first pair of stators, each having a first set of odd-numbered coil members distributed along a first radius of the stator, the stators disposed adjacent to opposing side portions of the rotor, wherein each coil member includes a core portion having an amorphous structure. In addition, a generator device for generating electrical energy includes interchangeable rotor and stator pairs to provide variable voltage/current/frequency outputs.
摘要翻译：一种用于产生电能的发电机装置包括转子，该转子具有沿着转子的第一半径分布的第一组偶数的磁源，以及第一对定子，每个定子具有分布在其上的第一组奇数线圈构件所述定子的第一半径，所述定子邻近所述转子的相对的侧部设置，其中每个线圈构件包括具有非晶结构的芯部。此外，用于产生电能的发电机装置包括可互换的转子和定子对，以提供可变电压/电流/频率输出。

40. 发明申请

US20060118785A1 Techniques for patterning features in semiconductor devices 有权
公开(公告)号：US20060118785A1
公开(公告)日：2006-06-08
申请号：US11337411
申请日：2006-01-23
申请人： Scott Allen , Katherina Babich , Steven Holmes , Arpan Mahorowala , Dirk Pfeiffer , Richard Wise
发明人： Scott Allen , Katherina Babich , Steven Holmes , Arpan Mahorowala , Dirk Pfeiffer , Richard Wise
IPC分类号： H01L23/58
CPC分类号： H01L21/31144 , H01L21/0276 , H01L21/0337 , H01L21/0338 , H01L21/31116 , Y10T428/24802 , Y10T428/24926
摘要： Techniques for semiconductor processing are provided. In one aspect, a method for patterning one or more features in a semiconductor device comprises the following step. At least one critical dimension of the one or more features is reduced during etching of the antireflective material. A lithographic structure is also provided.

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