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31. 发明授权

US07579870B2 Level shifter 有权
标题翻译：电平移位器
公开(公告)号：US07579870B2
公开(公告)日：2009-08-25
申请号：US11976671
申请日：2007-10-26
申请人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
发明人： Akinori Matsumoto , Shiro Sakiyama , Takashi Morie
IPC分类号： H03K19/0175
CPC分类号： H03K3/35613
摘要： Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
摘要翻译：输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

32. 发明申请

US20090284282A1 LEVEL SHIFTER 有权
标题翻译：水平变化
公开(公告)号：US20090284282A1
公开(公告)日：2009-11-19
申请号：US12510718
申请日：2009-07-28
申请人： Akinori MATSUMOTO , Shiro Sakiyama , Takashi Morie
发明人： Akinori MATSUMOTO , Shiro Sakiyama , Takashi Morie
IPC分类号： H03K19/0175 , H03L5/00
CPC分类号： H03K3/35613
摘要： Input transistors have sources which are connected to a first input reference node and gates to which a pair of input signals are input. Input-side voltage relaxing transistors have sources connected to drains of the pair of input transistors and gates connected to a second input reference node. Output-side voltage relaxing transistors have sources connected to output nodes, gates connected to a first output reference node, and drains connected to drains of the input-side voltage relaxing transistors. First and second inverter circuits are in correspondence with the output nodes, and are connected between second and third output reference nodes. Each of the first and second inverter circuits also supplies a voltage at one of the second and third output reference nodes to its corresponding one of the output nodes, depending on a voltage at its non-corresponding one of the output nodes.
摘要翻译：输入晶体管具有连接到输入一对输入信号的第一输入参考节点和栅极的源极。输入侧电压松弛晶体管具有连接到一对输入晶体管的漏极和连接到第二输入参考节点的栅极的源极。输出侧电压松弛晶体管具有连接到输出节点的源极，连接到第一输出参考节点的栅极和连接到输入侧电压松弛晶体管的漏极的漏极。第一和第二反相器电路与输出节点对应，并连接在第二和第三输出参考节点之间。第一和第二反相器电路中的每一个还根据其非对应的输出节点之间的电压将第二和第三输出参考节点中的一个上的电压提供给其对应的一个输出节点。

33. 发明申请

US20130009796A1 CLOCK GENERATOR CIRCUIT FOR SUCCESSIVE APPROXIMATIOM ANALOG TO-DIGITAL CONVERTER 审中-公开
标题翻译：时钟发生器电路，用于成功的近似模拟数字转换器
公开(公告)号：US20130009796A1
公开(公告)日：2013-01-10
申请号：US13620473
申请日：2012-09-14
申请人： Shiro Sakiyama , Akinori Matsumoto , Yusuke Tokunaga , Ichiro Kuwabara
发明人： Shiro Sakiyama , Akinori Matsumoto , Yusuke Tokunaga , Ichiro Kuwabara
IPC分类号： H03M1/38
CPC分类号： H03M1/0624 , H03M1/462
摘要： A sampling clock generator generates a sampling clock based on a reference clock and an internal clock. An internal clock generator causes, during a period in which the sampling clock is at a second voltage level, the internal clock to transition from a first voltage level to a second voltage level when a first comparison signal and a second comparison signal transition to voltage levels different from each other, and the internal clock to transition from the second voltage level to the first voltage level after a variable delay time has elapsed when the first and second comparison signals transition to a same voltage level. A delay controller controls the variable delay time in the internal clock generator so that the ratio of a period in which the sampling clock is at a first voltage level to a period of the reference clock approaches a predetermined ratio.
摘要翻译：采样时钟发生器基于参考时钟和内部时钟生成采样时钟。当第一比较信号和第二比较信号转换到电压电平时，内部时钟发生器在采样时钟处于第二电压电平的时段期间使内部时钟从第一电压电平转变到第二电压电平并且当第一和第二比较信号转变到相同电压电平时，在经过可变延迟时间之后，内部时钟从第二电压电平转变到第一电压电平。延迟控制器控制内部时钟发生器中的可变延迟时间，使得采样时钟处于第一电压电平的周期与参考时钟的周期之间的比率接近预定比率。

34. 发明授权

US07876166B2 Coupled ring oscillator and method for laying out the same 有权
标题翻译：耦合环形振荡器及其布置方法
公开(公告)号：US07876166B2
公开(公告)日：2011-01-25
申请号：US12831715
申请日：2010-07-07
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

35. 发明申请

US20050077955A1 Low-pass filter for a pll, phase-locked loop and semiconductor integrated circuit 失效
标题翻译：低通滤波器，用于pll，锁相环和半导体集成电路
公开(公告)号：US20050077955A1
公开(公告)日：2005-04-14
申请号：US10500875
申请日：2003-05-22
申请人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
发明人： Shiro Dosho , Naoshi Yanagisawa , Masaomi Toyama , Keijiro Umehara , Masahiro Fukui , Takefumi Yoshikawa , Toru Iwata , Shiro Sakiyama , Ryoichi Suzuki
IPC分类号： H03H11/12 , H03H11/04 , H03L7/08 , H03L7/081 , H03L7/089 , H03L7/093 , H03L7/107 , H03B1/00
CPC分类号： H03L7/0812 , H03L7/0891 , H03L7/0893 , H03L7/0896 , H03L7/093
摘要： The invention provides a low-pass filter suitably used as a loop filter for a PLL or a DLL that has a filtering characteristic equivalent to that of a conventional one and can be realized in a smaller circuit area. The low-pass filter includes first filtering means (31) for accepting, as an input, an input signal to the low-pass filter and outputting a first voltage; a circuit element (311) included in the first filtering means (31) for allowing a first current to flow in accordance with the first voltage; current generating means (32) for generating a second current at a given rate to the first current; second filtering means (33) for accepting, as an input, the second current and outputting a second voltage; and adding means (34) for adding the first voltage and the second voltage and outputting an output signal of the low-pass filter, in which the second current is set to be smaller than the first current.
摘要翻译：本发明提供一种适合用作PLL或DLL的环路滤波器的低通滤波器，其具有与常规滤波特性相同的滤波特性，并且可以在较小的电路面积中实现。低通滤波器包括第一滤波装置（31），用于接收输入到低通滤波器的输入信号作为输入，并输出第一电压; 包括在第一过滤装置（31）中的用于允许第一电流根据第一电压流动的电路元件（311）电流产生装置（32），用于以给定的速率产生与第一电流的第二电流; 第二滤波装置（33），用于接受第二电流作为输入并输出第二电压; 以及添加装置（34），用于将第一电压和第二电压相加，并输出低通滤波器的输出信号，其中第二电流被设置为小于第一电流。

36. 发明授权

US5751142A Reference voltage supply circuit and voltage feedback circuit 失效
标题翻译：参考电压电路和电压反馈电路
公开(公告)号：US5751142A
公开(公告)日：1998-05-12
申请号：US795906
申请日：1997-03-04
申请人： Shiro Dosho , Shiro Sakiyama , Masakatsu Maruyama , Masatoshi Matsushita , Koji Mochizuki
发明人： Shiro Dosho , Shiro Sakiyama , Masakatsu Maruyama , Masatoshi Matsushita , Koji Mochizuki
IPC分类号： G05F3/24 , G05F3/26 , G05F3/20
CPC分类号： G05F3/247 , G05F3/262 , Y10S323/901
摘要： A reference voltage output terminal of first and second reference voltage generating circuits is connected to a first current input terminal of a current mirror circuit of an operational amplifier by a diode element. At the time of start-up, a reference voltage generated on the reference voltage output terminal is 0 V. Consequently, a current flows to the diode element and an offset voltage Voff is generated on the operational amplifier so that a malfunction point is caused to disappear. Accordingly, in the case where a normal operation point on which a reference voltage having an expected value is generated and a malfunction point on which an operation is stabilized with a reference voltage having a value less than the expected value are present, the generated reference voltage is raised at the time of start-up, passes through the malfunction point to reach an expected voltage value on the normal operation point and becomes stabilized. In this state, the diode element is cut off so that the offset voltage Voff is caused to disappear.
摘要翻译：第一和第二参考电压产生电路的参考电压输出端通过二极管元件连接到运算放大器的电流镜电路的第一电流输入端。在启动时，在基准电压输出端子上产生的基准电压为0V。因此，电流流向二极管元件，并在运算放大器上产生偏移电压Voff，使得产生故障点消失。因此，在存在具有预期值的基准电压的正常工作点和存在具有小于预期值的参考电压使运行稳定的故障点的情况下，产生的基准电压在启动时升高，通过故障点达到正常工作点的预期电压值并稳定。在这种状态下，二极管元件被切断，使偏移电压Voff消失。

37. 发明申请

US20100271142A1 COUPLED RING OSCILLATOR AND METHOD FOR LAYING OUT THE SAME 有权
标题翻译：耦合振荡器及其相结合的方法
公开(公告)号：US20100271142A1
公开(公告)日：2010-10-28
申请号：US12831715
申请日：2010-07-07
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

38. 发明授权

US07777580B2 Coupled ring oscillator and method for laying out the same 有权
标题翻译：耦合环形振荡器及其布置方法
公开(公告)号：US07777580B2
公开(公告)日：2010-08-17
申请号：US11884270
申请日：2006-05-25
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中m×n个相位耦合电路（30）点在某一相位模式下，相互连接形成一个回路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

39. 发明授权

US5550544A Signal converter, noise shaper, AD converter and DA converter 失效
标题翻译：信号转换器，噪声整形器，AD转换器和DA转换器
公开(公告)号：US5550544A
公开(公告)日：1996-08-27
申请号：US200493
申请日：1994-02-23
申请人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
发明人： Shiro Sakiyama , Shiro Dosho , Masakatsu Maruyama , Hiroyuki Nakahira , Toshiyuki Shono , Akira Matsuzawa
IPC分类号： H03M3/00 , H03M1/00
CPC分类号： H03M3/424 , H03M3/456
摘要： The present invention provides a first-order delta-sigma AD converter adapted to conduct noise shaping and having a quantizer arranged such that, when the amplitude of an input signal entered into the quantizer is small, the amplitude of a difference signal between the input signal entered into the quantizer and an output signal therefrom, is small. It is therefore possible to achieve an efficient AD- or DA-converter reduced in power consumption, which satisfies the transmission characteristics of the specifications of CCITT G.714 based on a method of PCM-encoding an audio frequency band signal stipulated in the specifications of CCITT G.711.
摘要翻译：本发明提供了一种适用于进行噪声整形并具有量化器的一级Δ-ΣAD转换器，其被布置为使得当输入到量化器的输入信号的幅度较小时，输入信号之间的差信号的幅度进入量化器并且其输出信号很小。因此，可以实现功率消耗降低的有效的AD转换器或DA转换器，该功率消耗满足CCITT G.714的规格的传输特性，该方法基于对编码 CCITT G.711。

40. 发明申请

US20080068101A1 Coupled Ring Oscillator and Method for Laying Out the Same 有权
标题翻译：耦合振荡器及其放置方法
公开(公告)号：US20080068101A1
公开(公告)日：2008-03-20
申请号：US11884270
申请日：2006-05-25
申请人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
发明人： Shiro Dosho , Shiro Sakiyama , Noriaki Takeda
IPC分类号： H03K3/03
CPC分类号： H03K3/0315
摘要： A coupled ring oscillator includes n ring oscillators (20) each including m inverter circuits (10), and a phase-coupling loop (40) in which m×n phase-coupling circuits (30), each of which couples signal phases at two points in a certain phase mode, are connected with each other to form a loop. Connection points at which the inverter circuits (10) are connected with each other and the connection points at which the phase-coupling circuits (30) are connected with each other are connected bijectively; and each of the inverter circuits (10) is connected between two points that divide the phase-coupling circuits (30) into two parts at a certain ratio.
摘要翻译：耦合环形振荡器包括n个环形振荡器（20），每个环形振荡器（20）包括m个逆变器电路（10）和相位耦合回路（40），其中mxn个相位耦合电路（30）一定的相位模式相互连接形成一个环路。逆变器电路（10）彼此连接的连接点和相位耦合电路（30）彼此连接的连接点彼此连接; 并且每个逆变器电路（10）连接在将相耦合电路（30）以一定比例分成两部分的两个点之间。

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