专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

32. 发明授权

US5336950A Configuration features in a configurable logic array 失效
标题翻译：可配置逻辑阵列中的配置功能
公开(公告)号：US5336950A
公开(公告)日：1994-08-09
申请号：US15415
申请日：1993-02-08
申请人： Sanjay Popli , Scott Pickett , David Hawley , Shankar Moni , Rafael C. Camarota
发明人： Sanjay Popli , Scott Pickett , David Hawley , Shankar Moni , Rafael C. Camarota
IPC分类号： H03K17/22 , H03K19/003 , H03K19/173 , H03K19/177
CPC分类号： H03K19/17736 , H03K17/223 , H03K19/00361 , H03K19/1736 , H03K19/17704 , H03K19/17728
摘要： The present invention is directed to various configuration features of a logic array that includes a plurality of individually configurable logic cells arranged in a matrix. These features include reconfiguration logic for reconfiguring logic cells in a selected portion of the matrix using a window-based protocol. The array also includes configuration data storage means for storing configuration data utilizable for configuring the logic elements, wherein each logic element includes a working data storage register, and reset circuitry for modifying the configuration data without modifying the working data. The array further includes read disable circuitry and write disable circuitry for disabling read access and write access, respectively, to the configuration data. The array further includes a comparison protocol mechanism for checking the configuration data against data on the array pins. The array further includes a configuration circuit for generating external addresses and that can be controlled through a data configuration file fetched from an external storage medium.
摘要翻译：本发明涉及包括以矩阵形式布置的多个可单独配置的逻辑单元的逻辑阵列的各种配置特征。这些特征包括用于使用基于窗口的协议来重新配置矩阵的选定部分中的逻辑单元的重配置逻辑。该阵列还包括用于存储可用于配置逻辑元件的配置数据的配置数据存储装置，其中每个逻辑元件包括工作数据存储寄存器和用于在不修改工作数据的情况下修改配置数据的复位电路。该阵列还包括分别用于禁用对配置数据的读取和写入访问的读取禁止电路和写入禁止电路。该阵列还包括用于根据阵列引脚上的数据检查配置数据的比较协议机制。阵列还包括用于生成外部地址并且可以通过从外部存储介质取出的数据配置文件进行控制的配置电路。

IPRDB

热门服务

关于我们

友情链接

联系方式