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31. 发明申请

US20110068411A1 Block Contact Plugs for MOS Devices 有权
标题翻译： MOS器件的块式触点插头
公开(公告)号：US20110068411A1
公开(公告)日：2011-03-24
申请号：US12789046
申请日：2010-05-27
申请人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
发明人： Sey-Ping Sun , Chih-Hao Chang , Chao-An Jong , Tsung-Lin Lee , Chung-Ju Lee , Chin-Hsiang Lin
IPC分类号： H01L29/78
CPC分类号： H01L21/76897 , H01L21/76804 , H01L21/76816 , H01L23/485 , H01L2924/0002 , H01L2924/00
摘要： An integrated circuit structure includes a semiconductor substrate; a gate stack overlying the semiconductor substrate; a gate spacer on a sidewall of the gate stack; a first contact plug having an inner edge contacting a sidewall of the gate spacer, and a top surface level with a top surface of the gate stack; and a second contact plug over and contacting the first contact plug. The second contact plug has a cross-sectional area smaller than a cross-sectional area of the first contact plug.
摘要翻译：集成电路结构包括半导体衬底; 覆盖半导体衬底的栅极堆叠; 在栅极堆叠的侧壁上的栅极间隔物; 具有接触所述栅极隔离物的侧壁的内边缘的第一接触插塞和具有所述栅极堆叠的顶表面的顶表面水平; 以及第二接触插头，并且与第一接触插塞接触。第二接触插塞的横截面积小于第一接触插塞的横截面面积。

32. 发明申请

US20100276761A1 Non-Planar Transistors and Methods of Fabrication Thereof 有权
标题翻译：非平面晶体管及其制造方法
公开(公告)号：US20100276761A1
公开(公告)日：2010-11-04
申请号：US12652947
申请日：2010-01-06
申请人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
发明人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7856 , H01L29/41791 , H01L29/66803 , H01L29/7839 , H01L29/785 , H01L2029/7858
摘要： Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
摘要翻译：描述了非平面晶体管及其制造方法。在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

33. 发明授权

US06955931B1 Method for detecting silicide encroachment of a gate electrode in a semiconductor arrangement 有权
标题翻译：用于检测半导体装置中栅电极的硅化物侵入的方法
公开(公告)号：US06955931B1
公开(公告)日：2005-10-18
申请号：US11053863
申请日：2005-02-10
申请人： David E. Brown , Sey-Ping Sun
发明人： David E. Brown , Sey-Ping Sun
IPC分类号： H01L21/336 , H01L21/66
CPC分类号： H01L29/7842 , H01L22/24 , H01L29/665 , H01L29/6653
摘要： A method of detecting silicide encroachment to the sidewalls of a gate electrode includes forming silicide at a device, with sidewall spacers defining a desired separation of the silicide from the sidewalls of the gate electrode. After silicide formation, the sidewall spacers are removed and line-of-sight monitoring is performed of the region previously obscured by the sidewall spacers, thereby permitting detection of silicide encroachment.
摘要翻译：检测硅化物侵入到栅电极的侧壁的方法包括在器件处形成硅化物，其中侧壁间隔物限定硅化物与栅电极的侧壁的期望间隔。在硅化物形成之后，去除侧壁间隔物，并且对由先前被侧壁间隔物遮蔽的区域进行视线监测，从而允许检测硅化物侵入。

34. 发明授权

US06372668B1 Method of forming silicon oxynitride films 有权
公开(公告)号：US06372668B1
公开(公告)日：2002-04-16
申请号：US09484603
申请日：2000-01-18
申请人： Sey-Ping Sun , Homi Nariman , Hartmut Ruelke
发明人： Sey-Ping Sun , Homi Nariman , Hartmut Ruelke
IPC分类号： H01L2131
摘要： The present invention is directed to a method of forming process layers comprised of silicon oxynitride. In one embodiment, the method comprises positioning a wafer in a process chamber, introducing silane and nitrous oxide into the chamber at a flow rate ratio ranging from approximately 2.6-3.8 silane to nitrous oxide, and generating a plasma in the chamber using a high frequency to low frequency power setting ratio ranging from approximately 1.2-1.8.

35. 发明授权

US06251800B1 Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance 失效
标题翻译：使用低功率，低压PECVD的超薄沉积栅介质形成，以改善半导体器件性能
公开(公告)号：US06251800B1
公开(公告)日：2001-06-26
申请号：US09227513
申请日：1999-01-06
申请人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
发明人： Sey-Ping Sun , Mark I. Gardner , Charles E. May
IPC分类号： H01L2131
CPC分类号： H01L21/28185 , C23C16/402 , H01L21/02164 , H01L21/02211 , H01L21/02274 , H01L21/0228 , H01L21/02332 , H01L21/02337 , H01L21/28194 , H01L21/31612
摘要： An ultrathin gate dielectric and a method for forming the same are provided. The gate dielectric is believed to allow enhanced performance of semiconductor devices including transistors and dual-gate memory cells. A low-power, low-pressure plasma-enhanced chemical vapor deposition (PECVD) method employing silane and nitrous oxide sources is used to deposit the dielectric. As compared to conventional PECVD deposition, the method uses lower silane and nitrous oxide flow rates, a more dilute silane in nitrogen mixture, a lower chamber pressure, and a lower radio frequency power density. These settings allow plasma conditions to stabilize so that deposition may be performed in time increments at least as short as 0.1 second, so that oxide thicknesses at least as small as one angstrom may be controllably deposited. The oxide is preferably deposited in portions at multiple substrate mounting positions in a deposition chamber. Combination of oxide portions in this manner is believed to reduce the density of pinholes in the oxide, and the low-power, low-pressure deposition conditions are further believed to reduce plasma damage to the oxide and reduce the density of trap states in the oxide. A rapid thermal anneal of the oxide may be performed after deposition, and may improve the quality of the interface between the oxide and the underlying semiconductor substrate.
摘要翻译：提供一种超薄栅极电介质及其形成方法。认为栅极电介质允许包括晶体管和双栅极存储器单元的半导体器件的增强的性能。使用采用硅烷和一氧化二氮源的低功率，低压等离子体增强化学气相沉积（PECVD）方法沉积电介质。与传统的PECVD沉积相比，该方法使用较低的硅烷和一氧化二氮流率，氮混合物中更稀的硅烷，较低的室压力和较低的射频功率密度。这些设置允许等离子体条件稳定，使得可以以至少短至0.1秒的时间增量执行沉积，使得至少小至一埃的氧化物厚度可以可控地沉积。优选在沉积室中的多个基板安装位置处部分地沉积氧化物。认为以这种方式组合氧化物部分可以降低氧化物中针孔的密度，并且进一步认为低功率，低压沉积条件可减少对氧化物的等离子体损伤并降低氧化物中陷阱态的密度。可以在沉积之后进行氧化物的快速热退火，并且可以提高氧化物和下面的半导体衬底之间的界面的质量。

36. 发明授权

US6140688A Semiconductor device with self-aligned metal-containing gate 有权
标题翻译：具有自对准含金属栅极的半导体器件
公开(公告)号：US6140688A
公开(公告)日：2000-10-31
申请号：US157627
申请日：1998-09-21
申请人： Mark I. Gardner , Sey-Ping Sun
发明人： Mark I. Gardner , Sey-Ping Sun
IPC分类号： H01L21/28 , H01L21/336 , H01L21/8234 , H01L21/8247 , H01L27/088 , H01L29/76
CPC分类号： H01L27/105 , H01L21/28061 , H01L21/28273 , H01L21/82345 , H01L27/088 , H01L27/11526 , H01L27/11531 , H01L27/11543 , H01L29/6659 , H01L29/66825 , H01L27/11529 , H01L29/66545
摘要： A semiconductor device is provided and formed using self-aligned metal-containing gates within a metal-oxide semiconductor (MOS) process. After forming junction regions within a semiconductor substrate, the gate conductor, or junction implant alignment structure, is at least partially removed to form a trench within a dielectric formed above the substrate. Upper surfaces of the transistor, except the upper surface of the gate conductor, are thereby protected by the dielectric. A metal-containing material can then be arranged within the trench, i.e., in the region removed of the gate conductor. The metal material can be formed either as a single layer or as multiple metal and/or dielectric layers interposed throughout the as-filled trench. The metal-filled trench formation occurs after high temperature cycles often associated with activating the previously implanted junctions or growing gate dielectrics. Thus, low-temperature metals such as copper or copper alloys can be used.
摘要翻译：在金属氧化物半导体（MOS）工艺中，使用自对准的含金属栅极提供并形成半导体器件。在半导体衬底中形成接合区域之后，至少部分去除栅极导体或结植入对准结构，以在衬底上形成的电介质内形成沟槽。除了栅极导体的上表面之外，晶体管的上表面被电介质保护。然后可以在沟槽内，即在去除栅极导体的区域中布置含金属的材料。金属材料可以形成为单层或多个金属和/或介电层插入整个填充的沟槽中。金属填充的沟槽形成在高温循环之后发生，通常与激活先前注入的结或生长栅极电介质相关联。因此，可以使用诸如铜或铜合金的低温金属。

37. 发明授权

US09589803B2 Gate electrode of field effect transistor 有权
标题翻译：场效应晶体管的栅电极
公开(公告)号：US09589803B2
公开(公告)日：2017-03-07
申请号：US13572494
申请日：2012-08-10
申请人： Neng-Kuo Chen , Clement Hsingjen Wann , Yi-An Lin , Chun-Wei Chang , Sey-Ping Sun
发明人： Neng-Kuo Chen , Clement Hsingjen Wann , Yi-An Lin , Chun-Wei Chang , Sey-Ping Sun
IPC分类号： H01L29/94 , H01L21/28 , H01L21/3105 , H01L29/66 , H01L21/8238 , H01L29/78 , H01L29/165
CPC分类号： H01L29/66545 , H01L21/28123 , H01L21/31053 , H01L21/3212 , H01L21/32134 , H01L21/32135 , H01L21/823807 , H01L21/823814 , H01L21/823821 , H01L29/165 , H01L29/6653 , H01L29/66636 , H01L29/66795 , H01L29/7848 , H01L29/785
摘要： This description relates to a gate electrode of a field effect transistor. An exemplary structure for a field effect transistor includes a substrate; a gate electrode over the substrate including a first top surface and a sidewall; a source/drain (S/D) region at least partially disposed in the substrate on one side of the gate electrode; a spacer on the sidewall distributed between the gate electrode and the S/D region; and a contact etch stop layer (CESL) adjacent to the spacer and further comprising a portion extending over the S/D region, wherein the portion has a second top surface substantially coplanar with the first top surface.
摘要翻译：该描述涉及场效应晶体管的栅电极。场效应晶体管的示例性结构包括：衬底; 位于所述基板上方的包括第一顶表面和侧壁的栅电极; 至少部分地设置在所述栅电极的一侧的所述衬底中的源极/漏极（S / D）区域; 在所述侧壁上的间隔物分布在所述栅电极和所述S / D区之间; 以及与所述间隔物相邻的接触蚀刻停止层（CESL），并且还包括在所述S / D区域上延伸的部分，其中所述部分具有与所述第一顶表面基本上共面的第二顶表面。

38. 发明授权

US09054194B2 Non-planar transistors and methods of fabrication thereof 有权
标题翻译：非平面晶体管及其制造方法
公开(公告)号：US09054194B2
公开(公告)日：2015-06-09
申请号：US12652947
申请日：2010-01-06
申请人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
发明人： Chih-Hang Tung , Chin-Hsiang Lin , Cheng-Hung Chang , Sey-Ping Sun
IPC分类号： H01L21/336 , H01L29/78 , H01L29/417 , H01L29/66
CPC分类号： H01L29/7856 , H01L29/41791 , H01L29/66803 , H01L29/7839 , H01L29/785 , H01L2029/7858
摘要： Non-planar transistors and methods of fabrication thereof are described. In an embodiment, a method of forming a non-planar transistor includes forming a channel region on a first portion of a semiconductor fin, the semiconductor fin having a top surface and sidewalls. A gate electrode is formed over the channel region of the semiconductor fin, and an in-situ doped semiconductor layer is grown on the top surface and the sidewalls of the semiconductor fin on opposing sides of the gate electrode using a selective epitaxial growth process. At least a part of the doped semiconductor layer is converted to form a dopant rich region.
摘要翻译：描述了非平面晶体管及其制造方法。在一个实施例中，形成非平面晶体管的方法包括在半导体鳍片的第一部分上形成沟道区域，所述半导体鳍片具有顶表面和侧壁。在半导体鳍片的沟道区域上形成栅电极，并且使用选择性外延生长工艺在栅电极的相对侧的半导体翅片的顶表面和侧壁上生长原位掺杂半导体层。掺杂半导体层的至少一部分被转换以形成掺杂剂浓度区域。

39. 发明授权

US08003459B2 Method for forming semiconductor devices with active silicon height variation 有权
标题翻译：用于形成具有活性硅高度变化的半导体器件的方法
公开(公告)号：US08003459B2
公开(公告)日：2011-08-23
申请号：US12691477
申请日：2010-01-21
申请人： David E. Brown , Hans Van Meer , Sey-Ping Sun
发明人： David E. Brown , Hans Van Meer , Sey-Ping Sun
IPC分类号： H01L21/8238
CPC分类号： H01L29/0684 , H01L21/84 , H01L27/1203
摘要： A method for forming different active thicknesses on the same silicon layer includes masking the silicon layer and exposing selected regions of the silicon layer. The thickness of the silicon layer at the exposed regions is changed, either by adding silicon or subtracting silicon from the layer at the exposed regions. Once the mask is removed, the silicon layer has regions of different active thicknesses, respectively suitable for use in different types of devices, such as diodes and transistors.
摘要翻译：在同一硅层上形成不同有源厚度的方法包括掩蔽硅层并暴露硅层的选定区域。通过在曝光区域从层中添加硅或从中减去硅来改变暴露区域处的硅层的厚度。一旦去除掩模，硅层就具有不同有源厚度的区域，分别适用于不同类型的器件，例如二极管和晶体管。

40. 发明申请

US20080173942A1 STRUCTURE AND METHOD OF MANUFACTURING A STRAINED FinFET WITH STRESSED SILICIDE 审中-公开
标题翻译：具有应力硅化物的应变FinFET的结构和方法
公开(公告)号：US20080173942A1
公开(公告)日：2008-07-24
申请号：US11625431
申请日：2007-01-22
申请人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
发明人： Huilong Zhu , Siddhartha Panda , Jay W. Strane , Sey-Ping Sun , Brian L. Tessier
IPC分类号： H01L29/786 , H01L21/336
CPC分类号： H01L29/785 , H01L29/66795
摘要： A stressed semiconductor structure including at least one FinFET device on a surface of a substrate, typically a buried insulating layer of an initial semiconductor-on-insulator substrate, is provided. In a preferred embodiment, the at least one FinFET device includes a semiconductor Fin that is located on an unetched portion of the buried insulator layer which has a raised height as compared to an adjacent and adjoining etched portion of the buried insulating layer. The semiconductor Fin includes a gate dielectric on its sidewalls and optionally a hard mask located on an upper surface thereof. The inventive structure also includes a gate conductor, which is located on the surface of the substrate, typically the buried insulating layer, and the gate conductor is at least laterally adjacent to the gate dielectric located on the sidewalls of the semiconductor Fin. A stressed silicide is located on the gate conductor, which introduces stress into the channel of the FinFET device. The stressed silicide memorizes the stress from a sacrificial stressed film that is formed prior to forming the stressed silicide. The stress type of the stressed film is introduced into the silicide during a silicide anneal step.
摘要翻译：提供了一种应力半导体结构，其包括在衬底的表面上的至少一个FinFET器件，通常是初始绝缘体上半导体衬底的掩埋绝缘层。在优选实施例中，所述至少一个FinFET器件包括位于所述掩埋绝缘体层的未蚀刻部分上的半导体Fin，所述半导体Fin与所述掩埋绝缘层的相邻和相邻蚀刻部分相比具有升高的高度。半导体鳍包括其侧壁上的栅极电介质和任选地位于其上表面上的硬掩模。本发明的结构还包括栅极导体，其位于衬底的表面上，通常为掩埋绝缘层，并且栅极导体至少横向邻近位于半导体Fin的侧壁上的栅极电介质。应力硅化物位于栅极导体上，其将应力引入FinFET器件的沟道中。应力硅化物记忆在形成应力硅化物之前形成的牺牲应力膜的应力。在硅化物退火步骤期间，将应力膜的应力类型引入到硅化物中。

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