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31. 发明申请

US20070052043A1 Multilayer gate electrode, semiconductor device having the same and method of fabricating the same 审中-公开
标题翻译：多层栅电极，与其相同的半导体器件及其制造方法
公开(公告)号：US20070052043A1
公开(公告)日：2007-03-08
申请号：US11516633
申请日：2006-09-07
申请人： Tae-Ho Cha , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Byung-Hee Kim
发明人： Tae-Ho Cha , Chang-Won Lee , Hee-Sook Park , Woong-Hee Sohn , Byung-Hee Kim
IPC分类号： H01L29/94 , H01L21/3205
CPC分类号： H01L21/823842 , H01L21/823828
摘要： Example embodiments relate to a multilayer gate electrode, a semiconductor device having the same and methods of fabricating the same. Other example embodiments relate to a semiconductor device with a multilayer gate electrode which is relatively stable at higher temperatures, has improved resistance characteristics and improved reliability, and methods of fabricating the same. The multilayer gate electrode may include a polycrystalline semiconductor layer on the gate insulating layer and doped with conductive type impurities, an ohmic contact layer on the polycrystalline semiconductor layer and including tungsten (W1−x) and non-tungsten metal (Mx, x=about 0.01 to about 0.55), a metal barrier layer on the ohmic contact layer and a refractory metal layer on the metal barrier layer. The semiconductor device including a conductive type transistor may include a semiconductor substrate, a conductive type source/drain region in the semiconductor substrate, a gate insulating layer on a channel region between the source/drain regions and the multilayer gate electrode.
摘要翻译：示例性实施例涉及多层栅电极，具有该多层栅电极的半导体器件及其制造方法。其他示例性实施例涉及具有多层栅电极的半导体器件，其在较高温度下相对稳定，具有改善的电阻特性和改善的可靠性，及其制造方法。多层栅电极可以包括在栅极绝缘层上并掺杂有导电类型杂质的多晶半导体层，多晶半导体层上的欧姆接触层，并且包括钨（W 1-x N）钨金属（M x x x，x =约0.01至约0.55），欧姆接触层上的金属阻挡层和金属阻挡层上的难熔金属层。包括导电型晶体管的半导体器件可以包括半导体衬底，半导体衬底中的导电型源极/漏极区域，在源极/漏极区域和多层栅极电极之间的沟道区域上的栅极绝缘层。

32. 发明授权

US07148100B2 Methods of forming electronic devices including high-k dielectric layers and electrode barrier layers 有权
标题翻译：形成包括高k电介质层和电极阻挡层的电子器件的方法
公开(公告)号：US07148100B2
公开(公告)日：2006-12-12
申请号：US10969564
申请日：2004-10-20
申请人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
发明人： Byung-Hee Kim , Gil-Heyun Choi , Kyung-In Choi , Chang-Won Lee
IPC分类号： H01L21/8238
CPC分类号： H01L21/28088 , H01L21/28194 , H01L21/823857 , H01L29/4966 , H01L29/517 , H01L29/6656 , H01L29/66583 , H01L29/6659 , H01L29/7833
摘要： Methods of forming a microelectronic device can include providing a gate dielectric layer on a channel region of a semiconductor substrate wherein the gate dielectric layer is a high-k dielectric material. A gate electrode barrier layer can be provided on the gate dielectric layer opposite the channel region of the semiconductor substrate, and a gate electrode metal layer can be provided on the gate electrode barrier layer opposite the channel region of the semiconductor substrate. The gate electrode barrier layer and the gate electrode metal layer can be formed of different materials. Moreover, the gate electrode metal layer can include a first material and the gate electrode barrier layer can include a second material, and the first material can have a lower electrical resistivity than the second material.
摘要翻译：形成微电子器件的方法可以包括在半导体衬底的沟道区上提供栅极电介质层，其中栅极电介质层是高k电介质材料。可以在与半导体衬底的沟道区相对的栅极电介质层上设置栅电极阻挡层，并且可以在与半导体衬底的沟道区相对的栅极电极阻挡层上设置栅电极金属层。栅电极阻挡层和栅电极金属层可以由不同的材料形成。此外，栅电极金属层可以包括第一材料，并且栅电极阻挡层可以包括第二材料，并且第一材料可以具有比第二材料更低的电阻率。

33. 发明申请

US20060270204A1 Methods of fabricating a semiconductor device having a metal gate pattern 有权
标题翻译：制造具有金属栅极图案的半导体器件的方法
公开(公告)号：US20060270204A1
公开(公告)日：2006-11-30
申请号：US11498195
申请日：2006-08-03
申请人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
发明人： Ja-Hum Ku , Chang-Won Lee , Seong-Jun Heo , Sun-Pil Youn , Sung-Man Kim
IPC分类号： H01L21/4763 , H01L21/3205
CPC分类号： H01L21/823437 , H01L21/28247 , H01L29/4941 , H01L29/6656
摘要： A method of fabricating a semiconductor device having a metal gate pattern is provided in which capping layers are used to control the relative oxidation rates of portions of the metal gate pattern during a oxidation process. The capping layer may be a multilayer structure and may be etched to form insulating spacers on the sidewalls of the metal gate pattern. The capping layer(s) allow the use of a selective oxidation process, which may be a wet oxidation process utilizing partial pressures of both H2O and H2 in an H2-rich atmosphere, to oxidize portions of the substrate and metal gate pattern while suppressing the oxidation of metal layers that may be included in the metal gate pattern. This allows etch damage to the silicon substrate and edges of the metal gate pattern to be reduced while substantially maintaining the original thickness of the gate insulating layer and the conductivity of the metal layer(s).
摘要翻译：提供一种制造具有金属栅极图案的半导体器件的方法，其中使用覆盖层来控制氧化过程中金属栅极图案的部分的相对氧化率。覆盖层可以是多层结构，并且可以被蚀刻以在金属栅极图案的侧壁上形成绝缘间隔物。封盖层允许使用选择性氧化工艺，其可以是使用H 2 H 2 O和H 2 H 2的分压的H氧化方法 2极化气氛，以便在抑制可能包含在金属栅极图案中的金属层的氧化的同时氧化基板和金属栅极图案的部分。这允许对硅衬底的蚀刻损伤和金属栅极图案的边缘减小，同时基本上保持栅极绝缘层的原始厚度和金属层的导电性。

34. 发明申请

US20060115967A1 Methods of manufacturing a semiconductor device 审中-公开
标题翻译：制造半导体器件的方法
公开(公告)号：US20060115967A1
公开(公告)日：2006-06-01
申请号：US11246791
申请日：2005-10-07
申请人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
发明人： Hee-Sook Park , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Jong-Ryeol Yoo , Dong-Chan Lim , Jae-Hwa Park , Sun-Pil Youn , Woong-Hee Sohn
IPC分类号： H01L21/8238 , H01L21/425
CPC分类号： H01L21/823828
摘要： In a method of manufacturing a semiconductor device including a polysilicon layer on which a heat treatment is performed in hydrogen atmosphere, a preliminary polysilicon layer is formed on a semiconductor substrate. Fluorine (F) impurities are implanted onto the preliminary polysilicon layer, so that the preliminary polysilicon layer is formed into a polysilicon layer. A main heat treatment is performed on the polysilicon layer, thereby preventing a void caused by the fluorine (F) in the polysilicon layer. A subsidiary heat treatment is further performed on the polysilicon layer prior to the main heat treatment, thereby activating dopants in the polysilicon layer. Electrical characteristics and performance of a semiconductor device are improved since the void is sufficiently prevented in the polysilicon layer.
摘要翻译：在制造包括在氢气氛中进行热处理的多晶硅层的半导体器件的方法中，在半导体衬底上形成初步多晶硅层。将氟（F）杂质注入到初步多晶硅层上，使得初步多晶硅层形成为多晶硅层。在多晶硅层上进行主要的热处理，从而防止由多晶硅层中的氟（F）引起的空隙。在主要热处理之前在多晶硅层上进一步进行辅助热处理，由此激活多晶硅层中的掺杂剂。改善了半导体器件的电特性和性能，因为在多晶硅层中充分防止了空隙。

35. 发明申请

US20060079075A1 Gate structures with silicide sidewall barriers and methods of manufacturing the same 审中-公开
标题翻译：具有硅化物侧壁障碍的门结构及其制造方法
公开(公告)号：US20060079075A1
公开(公告)日：2006-04-13
申请号：US11201736
申请日：2005-08-11
申请人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
发明人： Chang-Won Lee , Sun-Pil Youn , Gil-Heyun Choi , Byung-Hak Lee , Hee-Sook Park , Dong-Chan Lim , Jong-Ryeol Yoo , Woong-Hee Sohn
IPC分类号： H01L21/3205
CPC分类号： H01L21/28061 , H01L29/4958 , H01L29/517
摘要： A gate structure includes a gate insulation layer on a substrate, a polysilicon layer pattern on the gate insulation layer, a composite metal layer pattern on the polysilicon layer pattern, and a metal silicide layer pattern on a sidewall of the composite metal layer pattern.
摘要翻译：栅极结构包括在衬底上的栅极绝缘层，栅极绝缘层上的多晶硅层图案，多晶硅层图案上的复合金属层图案以及复合金属层图案的侧壁上的金属硅化物层图案。

36. 发明申请

US20050266665A1 Methods of manufacturing semiconductor devices with gate structures having an oxide layer on the sidewalls thereof and related processing apparatus 审中-公开
标题翻译：制造具有在其侧壁上具有氧化物层的栅极结构的半导体器件的方法和相关的处理装置
公开(公告)号：US20050266665A1
公开(公告)日：2005-12-01
申请号：US11141401
申请日：2005-05-31
申请人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
发明人： Sun-Pil Youn , Gil-Heyun Choi , Chang-Won Lee , Byung-Hak Lee , Hee-Sook Park , Woong-Hee Shon , Jong-Ryeol Yoo
IPC分类号： H01L21/336 , H01L21/28 , H01L21/3205 , H01L21/321
CPC分类号： H01L21/28247 , H01L21/28061 , H01L21/32105
摘要： In a method of manufacturing a semiconductor device, a gate structure having a conductive layer pattern is formed on a substrate. The gate structure is then annealed. Oxygen radicals are applied to the gate structure to form an oxide layer on a sidewall of the conductive layer pattern.
摘要翻译：在制造半导体器件的方法中，在衬底上形成具有导电层图案的栅极结构。然后将栅极结构退火。将氧自由基施加到栅极结构以在导电层图案的侧壁上形成氧化物层。

37. 发明申请

US20130156733A1 INFLUENZA VIRUS POPULATIONS, METHODS OF USE AND METHODS OF MAKING THEREOF 审中-公开
标题翻译：流感病毒人群，使用方法及其制备方法
公开(公告)号：US20130156733A1
公开(公告)日：2013-06-20
申请号：US13721787
申请日：2012-12-20
申请人： Philip I. Marcus , John M. Ngunjiri , Margaret J. Sekellick , Chang-Won Lee
发明人： Philip I. Marcus , John M. Ngunjiri , Margaret J. Sekellick , Chang-Won Lee
IPC分类号： A61K35/76 , A61K38/21
CPC分类号： A61K35/76 , A61K38/21 , A61K39/12 , A61K39/145 , A61K2039/5254 , A61K2039/57 , C07K14/005 , C12N7/00 , C12N2760/16121 , C12N2760/16122 , C12N2760/16132 , C12N2760/16134 , C12N2760/16171 , C12N2999/002 , C12Q1/701 , A61K2300/00
摘要： Disclosed herein are live attenuated influenza virus compositions for inducing interferon comprising quantified subpopulations of interferon-inducing particles and defective-interfering particles. The live attenuated influenza virus compositions are particularly useful to induce interferon in an individual having or suspected of having a viral infection. Further, by infecting mammalian and avian cells with the live attenuated influenza virus compositions, the compositions optimized for mammalian or avian species can be selected based on the ratio of defective-interfering particles to interferon-inducing particles.
摘要翻译：本文公开了用于诱导干扰素的活减毒流感病毒组合物，其包含定量的干扰素诱导颗粒和缺陷干扰颗粒的亚群。活减毒流感病毒组合物特别可用于在具有或怀疑患有病毒感染的个体中诱导干扰素。此外，通过用活减毒流感病毒组合物感染哺乳动物和禽类细胞，可以基于缺陷干扰颗粒与干扰素诱导颗粒的比例来选择针对哺乳动物或鸟类物种优化的组合物。

38. 发明申请

US20110207232A1 WATER SOLUBLE PH RESPONSIVE FLUORESCENT NANOPARTICLES 审中-公开
标题翻译：水溶性PH响应荧光纳米颗粒
公开(公告)号：US20110207232A1
公开(公告)日：2011-08-25
申请号：US12778798
申请日：2010-05-12
申请人： Agnes Ostafin , Chang-Won Lee
发明人： Agnes Ostafin , Chang-Won Lee
IPC分类号： G01N21/00 , G01N21/76 , B23P17/04 , B82Y30/00
CPC分类号： G01N21/643 , B82Y15/00 , B82Y30/00 , G01N21/80 , G01N33/587 , G01N33/84 , G01N2021/6439 , G01N2201/06113 , H01J37/261 , Y10T29/49
摘要： A nano-pH sensor can include a nanoparticle having an outer surface functionalized by a carboxy functional group. The nanoparticle is reversibly aggregated as a function of pH and is generally non-toxic. A fluorometer can be oriented to expose the nanoparticles to a light source at a given wavelength. Further, the fluorometer can be configured to detect changes in fluorescence of the gold nanoparticle with changes in pH.
摘要翻译：纳米pH传感器可以包括具有由羧基官能团官能化的外表面的纳米颗粒。纳米颗粒作为pH的函数可逆地聚集并且通常是无毒的。荧光计可以被定向以将纳米颗粒暴露于给定波长的光源。此外，荧光计可以配置成随着pH的变化来检测金纳米颗粒的荧光变化。

39. 发明申请

US20110189846A1 METHODS OF MANUFACTURING NON-VOLATILE MEMORY DEVICES 审中-公开
标题翻译：制造非易失性存储器件的方法
公开(公告)号：US20110189846A1
公开(公告)日：2011-08-04
申请号：US13020979
申请日：2011-02-04
申请人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
发明人： Jeong Gil Lee , Chang-Won Lee , Sang-Woo Lee , Sun-Woo Lee , Ki-Hyun Hwang , Jae-Hwa Park , Eun-Ji Jung
IPC分类号： H01L21/28
CPC分类号： H01L21/28
摘要： A method of manufacturing a non-volatile memory device including a tunnel oxide layer, a preliminary charge storing layer and a dielectric layer on a semiconductor layer is disclosed. A first polysilicon layer is formed on the dielectric layer. A barrier layer and a second polysilicon layer are formed on the first polysilicon layer. The second polysilicon layer, the barrier layer, the first polysilicon layer, the dielectric layer, the preliminary charge storing layer and the tunnel oxide layer are patterned to form a tunnel layer pattern, a charge storing layer pattern, a dielectric layer pattern, a first control gate pattern, a barrier layer pattern and a second polysilicon pattern. A nickel layer is formed on the second polysilicon layer. Heat treatment is performed with respect to the second polysilicon pattern and the nickel layer to form a second control gate pattern including NiSi on the barrier layer pattern.
摘要翻译：公开了一种在半导体层上制造包括隧道氧化物层，初电电荷存储层和电介质层的非易失性存储器件的方法。在介电层上形成第一多晶硅层。在第一多晶硅层上形成阻挡层和第二多晶硅层。对第二多晶硅层，势垒层，第一多晶硅层，电介质层，初电电荷存储层和隧道氧化物层进行图案化以形成隧道层图案，电荷存储层图案，介电层图案，第一控制栅极图案，势垒层图案和第二多晶硅图案。在第二多晶硅层上形成镍层。对第二多晶硅图案和镍层进行热处理，以在阻挡层图案上形成包括NiSi的第二控制栅极图案。

40. 发明申请

US20090316071A1 Dual liquid crystal display device 有权
标题翻译：双液晶显示装置
公开(公告)号：US20090316071A1
公开(公告)日：2009-12-24
申请号：US12385511
申请日：2009-04-09
申请人： Kyu-Han Bae , Shawn Kim , James Kim , Chang-Won Lee , David Lee , Hwal Choi
发明人： Kyu-Han Bae , Shawn Kim , James Kim , Chang-Won Lee , David Lee , Hwal Choi
IPC分类号： G02F1/1347 , G02F1/13357
CPC分类号： G02F1/133615 , G02B6/0036 , G02B6/0048 , G02B6/0063 , G02B6/0088 , G02F1/133553 , G02F2001/133342
摘要： A dual liquid crystal display (LCD) device including a first LCD panel displaying an image on a first surface; a second LCD panel formed on the same substrate to display an image on a second surface; a light source disposed at an adjacent side under the first LCD panel; a light guide disposed under the first and second LCD panels and including a first light guide block corresponding to the first LCD panel and having dot patterns formed in a first surface and a second light guide block corresponding to the second LCD panel and having taper-cascade grooves formed on a first surface; and a housing settling the first and second LCD panels, the light source and the light guide and having an opening to correspond to an image display surface of the second LCD panel.
摘要翻译：一种双液晶显示器（LCD）装置，包括在第一表面上显示图像的第一LCD面板; 形成在同一基板上以在第二表面上显示图像的第二LCD面板; 设置在所述第一LCD面板的下方的相邻侧的光源; 布置在所述第一和第二LCD面板下方的光导体，并且包括与所述第一LCD面板对应的第一导光块，并且具有形成在第一表面中的点图案和对应于所述第二LCD面板的具有锥形级联的第二导光块形成在第一表面上的槽; 以及使所述第一和第二LCD面板，所述光源和所述导光体固定的壳体，并具有与所述第二LCD面板的图像显示面对应的开口。

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