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    • 32. 发明授权
    • Ferroelectric memory and electronic apparatus
    • 铁电存储器和电子设备
    • US06930339B2
    • 2005-08-16
    • US10105002
    • 2002-03-22
    • Takamitsu HiguchiSetsuya IwashitaHiromu MiyazawaKazumasa HasegawaEiji Natori
    • Takamitsu HiguchiSetsuya IwashitaHiromu MiyazawaKazumasa HasegawaEiji Natori
    • G11C11/22H01L21/8246H01L27/105H01L31/119
    • H01L27/105
    • The present invention relates to a ferroelectric memory having a matrix-type memory cell array which has a superior degree of integration, in which the angularity of the ferroelectric layer's hysteresis curve is improved, the production yield is increased and costs are reduced.A ferroelectric memory having improved angularity in the hysteresis curve, and superior memory characteristics, production yield and costs is realized as follows. Namely, a peripheral circuit chip and a memory cell array chip are engaged onto an inexpensive assembly base 300 such as glass or plastic. In memory cell array chip 200, a ferroelectric layer is made to undergo epitaxial growth on to a Si single crystal via a buffer layer and first signal electrode. As a result, a ferroelectric memory can be realized which has improved angularity in the hysteresis curve and superior memory characteristics, production yield, and cost.
    • 本发明涉及一种具有优异的集成度的矩阵式存储单元阵列的铁电存储器,其中提高了铁电层磁滞曲线的角度,提高了生产成本并降低了成本。 具有改善的滞后曲线的角度,优异的存储特性,生产成本和成本的铁电存储器实现如下。 也就是说,外围电路芯片和存储单元阵列芯片被接合到诸如玻璃或塑料的便宜的组装基座300上。 在存储单元阵列芯片200中,使铁电体层通过缓冲层和第一信号电极进行Si单晶的外延生长。 结果,可以实现具有改善的滞后曲线的角度和优异的记忆特性,产量和成本的铁电存储器。
    • 38. 发明授权
    • Substrate for electronic device, method for manufacturing substrate for electronic device, and electronic device
    • 电子设备用基板,电子设备用基板的制造方法以及电子设备
    • US07247551B2
    • 2007-07-24
    • US10968957
    • 2004-10-21
    • Takamitsu HiguchiSetsuya IwashitaHiromu Miyazawa
    • Takamitsu HiguchiSetsuya IwashitaHiromu Miyazawa
    • H01L21/44
    • C30B23/02C30B29/24C30B29/32H01L21/02197H01L21/02266H01L21/02304H01L21/31691H01L28/55H01L28/60H01L29/045H01L41/316
    • The invention provides a substrate for an electronic device including a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation and which contains a metal oxide having a perovskite structure, a method for manufacturing a substrate for an electronic device, and an electronic device provided with such a substrate for an electronic device. A substrate for an electronic device includes a Si substrate, a buffer layer which is formed by epitaxial growth on the Si substrate and which contains a metal oxide having a NaCl structure, and a conductive oxide layer which is formed by epitaxial growth with cubic crystal (100) orientation or pseudo-cubic crystal (100) orientation on the buffer layer and which contains a metal oxide having a perovskite structure. The Si substrate is preferably a (100) substrate or a (110) substrate from which a natural oxidation film is not removed. The buffer layer preferably has an average thickness of 10 nm or less.
    • 本发明提供了一种电子器件用基板,其包括通过外延生长而具有立方晶(100)取向或假立方晶体(100)取向形成的导电氧化物层,并且其包含具有钙钛矿结构的金属氧化物, 制造用于电子设备的基板,以及设置有这种电子设备用基板的电子设备。 用于电子器件的衬底包括Si衬底,通过在Si衬底上外延生长并且含有具有NaCl结构的金属氧化物形成的缓冲层和通过用立方晶体外延生长形成的导电氧化物层( 100)取向或假立方晶体(100)取向,并且其包含具有钙钛矿结构的金属氧化物。 Si衬底优选是不去除天然氧化膜的(100)衬底或(110)衬底。 缓冲层的平均厚度优选为10nm以下。