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    • 34. 发明授权
    • Image reject circuit using sigma-delta conversion
    • 使用Σ-Δ转换的图像抑制电路
    • US07418062B2
    • 2008-08-26
    • US11598035
    • 2006-11-13
    • Gary Smith
    • Gary Smith
    • H04L27/14
    • H03D3/007
    • In a digital IF downconversion circuit, in-phase and quadrature signal components are processed in the form of a single serial digital bit stream through a set of simple logic in combination with a reconstruction filter. A source digital oscillator supplying digital signal mixers employs an oversampled digital word of four bits in length, all of which are binary weighted, to achieve at least sixteen levels of accuracy for a sine wave mixing signal without significant phase or amplitude error. The mixer mixes the digitized serial bit stream according to the clock with output of a four-bit wide table representing the source oscillator and the in-phase and quadrature signals are recombined digitally, followed by binary weighting using weighted resistors coupled into a filter. Thus, image rejection is a digital function which is unaffected by resistor tolerance.
    • 在数字IF下变频电路中,通过与重建滤波器组合的一组简单逻辑,以单个串行数字位流的形式处理同相和正交信号分量。 提供数字信号混合器的源数字振荡器采用长度为四位的过采样数字字,所有这些都是二进制加权的,以实现正弦波混频信号的至少16级精度,而没有明显的相位或幅度误差。 混频器根据时钟将数字化的串行比特流与表示源振荡器的四位宽表的输出进行混合,同相和正交信号被数字重新组合,然后使用耦合到滤波器中的加权电阻进行二进制加权。 因此,图像抑制是不受电阻容限影响的数字功能。