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31. 发明申请

US20110108804A1 Maskless Process for Suspending and Thinning Nanowires 失效
标题翻译：用于悬浮和稀释纳米线的无掩模工艺
公开(公告)号：US20110108804A1
公开(公告)日：2011-05-12
申请号：US13006833
申请日：2011-01-14
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/775 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

32. 发明申请

US20100252810A1 GATE PATTERNING OF NANO-CHANNEL DEVICES 有权
标题翻译： NANO通道设备的门控方案
公开(公告)号：US20100252810A1
公开(公告)日：2010-10-07
申请号：US12417954
申请日：2009-04-03
申请人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
发明人： Nicholas C. M. Fuller , Sarunya Bangsaruntip , Guy Cohen , Sebastian U. Engelmann , Lidija Sekaric , Qingyun Yang , Ying Zhang
IPC分类号： H01L29/41 , H01L21/306 , H01L21/302
CPC分类号： H01L21/32137 , H01L29/0665 , H01L29/0673 , H01L29/66439 , Y10S977/762 , Y10S977/938
摘要： Methodologies and gate etching processes are presented to enable the fabrication of gate conductors of semiconductor devices, such as NFETs and/or PFETs, which are equipped with nano-channels. In one embodiment, a sacrificial spacer of equivalent thickness to the diameter of the gate nano-channel is employed and is deposited after patterning the gate conductor down to the gate dielectric. The residue gate material that is beneath the nano-channel is removed utilizing a medium to high density, bias-free, fluorine-containing or fluorine- and chlorine-containing isotropic etch process without compromising the integrity of the gate. In another embodiment, an encapsulation/passivation layer is utilized. In yet further embodiment, no sacrificial spacer or encapsulation/passivation layer is used and gate etching is performed in an oxygen and nitrogen-free ambient.
摘要翻译：提出了方法和栅极蚀刻工艺，以便制造配备有纳米通道的半导体器件（例如NFET和/或PFET）的栅极导体。在一个实施例中，使用与栅极纳米通道的直径相当厚度的牺牲间隔物，并且在将栅极导体图案化成栅极电介质之后进行沉积。使用中等至高密度，无偏压，含氟或含氟和含氯的各向同性蚀刻工艺除去纳米通道下面的残留物栅极材料，而不损害栅极的完整性。在另一个实施例中，使用封装/钝化层。在又一实施例中，不使用牺牲间隔物或封装/钝化层，并且在无氧和无氮的环境中进行栅极蚀刻。

33. 发明申请

US20100193770A1 Maskless Process for Suspending and Thinning Nanowires 有权
标题翻译：用于悬浮和稀释纳米线的无掩模工艺
公开(公告)号：US20100193770A1
公开(公告)日：2010-08-05
申请号：US12365623
申请日：2009-02-04
申请人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
发明人： Sarunya Bangsaruntip , Guy Cohen , Jeffrey W. Sleight
IPC分类号： H01L29/78 , H01L21/4763 , H01L21/84
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L21/02488 , H01L21/02532 , H01L21/02603 , H01L21/0262 , H01L21/02639 , H01L21/02667 , H01L29/0665 , H01L29/0673 , H01L29/42392 , H01L29/66439 , H01L29/78696 , Y10S977/762
摘要： Semiconductor-based electronic devices and techniques for fabrication thereof are provided. In one aspect, a device is provided comprising a first pad; a second pad and a plurality of nanowires connecting the first pad and the second pad in a ladder-like configuration formed in a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer, the nanowires having one or more dimensions defined by a re-distribution of silicon from the nanowires to the pads. The device can comprise a field-effect transistor (FET) having a gate surrounding the nanowires wherein portions of the nanowires surrounded by the gate form channels of the FET, the first pad and portions of the nanowires extending out from the gate adjacent to the first pad form a source region of the FET and the second pad and portions of the nanowires extending out from the gate adjacent to the second pad form a drain region of the FET.
摘要翻译：提供了基于半导体的电子器件及其制造技术。在一个方面，提供了一种包括第一垫的装置; 第二焊盘和多个纳米线，其以形成在掩埋氧化物（BOX）层上的绝缘体上硅（SOI）层中的梯形结构连接第一焊盘和第二焊盘，该纳米线具有一个或多个维度由硅从纳米线重新分配到焊盘。该器件可以包括具有围绕纳米线的栅极的场效应晶体管（FET），其中纳米线的部分由FET的栅极沟道围绕，第一焊盘和纳米线的部分从邻近第一焊盘形成FET的源极区域，并且第二焊盘和从与第二焊盘相邻的栅极延伸出的纳米线的部分形成FET的漏极区域。

34. 发明申请

US20130175503A1 Compressive (PFET) and Tensile (NFET) Channel Strain in Nanowire FETs Fabricated with a Replacement Gate Process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）通道应变
公开(公告)号：US20130175503A1
公开(公告)日：2013-07-11
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L29/775 , H01L21/336 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

35. 发明授权

US08492208B1 Compressive (PFET) and tensile (NFET) channel strain in nanowire FETs fabricated with a replacement gate process 有权
标题翻译：用替代栅极工艺制造的纳米线FET中的压电（PFET）和拉伸（NFET）沟道应变
公开(公告)号：US08492208B1
公开(公告)日：2013-07-23
申请号：US13344352
申请日：2012-01-05
申请人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
发明人： Guy Cohen , Michael A. Guillorn , Conal Eugene Murray
IPC分类号： H01L21/00 , H01L29/76
CPC分类号： H01L29/775 , B82Y10/00 , B82Y40/00 , H01L29/66439
摘要： A method of fabricating a FET device is provided which includes the following steps. Nanowires/pads are formed in a SOI layer over a BOX layer, wherein the nanowires are suspended over the BOX. A HSQ layer is deposited that surrounds the nanowires. A portion(s) of the HSQ layer that surround the nanowires are cross-linked, wherein the cross-linking causes the portion(s) of the HSQ layer to shrink thereby inducing strain in the nanowires. One or more gates are formed that retain the strain induced in the nanowires. A FET device is also provided wherein each of the nanowires has a first region(s) that is deformed such that a lattice constant in the first region(s) is less than a relaxed lattice constant of the nanowires and a second region(s) that is deformed such that a lattice constant in the second region(s) is greater than the relaxed lattice constant of the nanowires.
摘要翻译：提供一种制造FET器件的方法，其包括以下步骤。纳米线/焊盘形成在BOX层上的SOI层中，其中纳米线悬挂在BOX上。沉积围绕纳米线的HSQ层。围绕纳米线的HSQ层的一部分交联，其中交联导致HSQ层的一部分收缩，从而诱导纳米线中的应变。形成一个或多个保持在纳米线中诱发的应变的栅极。还提供了一种FET器件，其中每个纳米线具有变形的第一区域，使得第一区域中的晶格常数小于纳米线的松弛晶格常数和第二区域，其变形使得第二区域中的晶格常数大于纳米线的松弛晶格常数。

36. 发明申请

US20140075258A1 ITERATIVE RECEIVER LOOP 有权
标题翻译：迭代接收器环路
公开(公告)号：US20140075258A1
公开(公告)日：2014-03-13
申请号：US13612911
申请日：2012-09-13
申请人： Mor Miller , Amit Steinberg , Daniel Wajcer , Dan Peleg , Guy Cohen
发明人： Mor Miller , Amit Steinberg , Daniel Wajcer , Dan Peleg , Guy Cohen
IPC分类号： H03M13/00
CPC分类号： H04L1/005 , H04L1/0047 , H04L1/0057 , H04L27/2655 , H04L27/266 , H04L27/2665 , H04L27/2679 , H04L27/2689 , H04L2001/0093 , H04L2027/0055 , H04L2027/0067
摘要： A method includes receiving a signal, which carries data that is encoded with an Error Correction Code (ECC), and correcting the received signal with an adaptive receiver loop. Soft input metrics for the data are computed over the corrected signal. The ECC is decoded using a decoder, which estimates soft output metrics based on the soft input metrics, by operating the decoder in an alternating pattern of external iterations that update one or more of the soft input metrics based on one or more of the soft output metrics, and internal iterations that update the soft output metrics but not the soft input metrics. The adaptive receiver loop is adjusted in a schedule that is defined relative to the pattern of the external and the internal iterations of the decoder.
摘要翻译：一种方法包括接收携带用纠错码（ECC）编码的数据的信号，并用自适应接收机环路校正接收到的信号。通过校正信号计算数据的软输入度量。使用解码器对ECC进行解码，解码器通过以基于软输出中的一个或多个更新一个或多个软输入度量的外部迭代的交替模式操作解码器来基于软输入度量来估计软输出量度指标和内部迭代更新软输出指标，而不是软输入指标。在相对于解码器的外部和内部迭代的模式定义的调度中调整自适应接收器环路。

37. 发明授权

US08546269B2 Top-down nanowire thinning processes 失效
标题翻译：自上而下的纳米线稀疏过程
公开(公告)号：US08546269B2
公开(公告)日：2013-10-01
申请号：US12417936
申请日：2009-04-03
申请人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
发明人： Tymon Barwicz , Guy Cohen , Lidija Sekaric , Jeffrey Sleight
IPC分类号： H01L21/302 , H01L21/461 , H01L29/06
CPC分类号： H01L21/02238 , B82Y10/00 , B82Y30/00 , H01L21/02255 , H01L21/30604 , H01L29/0665 , H01L29/0676 , H01L29/42392 , H01L29/775 , H01L29/78696
摘要： Techniques for fabricating nanowire-based devices are provided. In one aspect, a method for fabricating a semiconductor device is provided comprising the following steps. A wafer is provided having a silicon-on-insulator (SOI) layer over a buried oxide (BOX) layer. Nanowires and pads are etched into the SOI layer to form a ladder-like structure wherein the pads are attached at opposite ends of the nanowires. The BOX layer is undercut beneath the nanowires. The nanowires and pads are contacted with an oxidizing gas to oxidize the silicon in the nanowires and pads under conditions that produce a ratio of a silicon consumption rate by oxidation on the nanowires to a silicon consumption rate by oxidation on the pads of from about 0.75 to about 1.25. An aspect ratio of width to thickness among all of the nanowires may be unified prior to contacting the nanowires and pads with the oxidizing gas.
摘要翻译：提供了制造基于纳米线的器件的技术。一方面，提供一种制造半导体器件的方法，包括以下步骤。提供了在掩埋氧化物（BOX）层上方具有绝缘体上硅（SOI）层的晶片。将纳米线和焊盘蚀刻到SOI层中以形成阶梯状结构，其中焊盘附着在纳米线的相对端。 BOX层在纳米线下面被切下。纳米线和焊盘与氧化气体接触，以在通过氧化在纳米线上产生硅消耗速率与硅消耗速率之比的条件下，在纳米线和焊盘中氧化硅，焊盘上的氧化从约0.75降至约1.25。在使纳米线和焊盘与氧化气体接触之前，可以统一所有纳米线中的宽度与厚度的纵横比。

38. 发明授权

US08494016B2 Mode locked laser system 有权
标题翻译：模式锁定激光系统
公开(公告)号：US08494016B2
公开(公告)日：2013-07-23
申请号：US13000015
申请日：2009-07-29
申请人： Yoram Karni , Guy Cohen
发明人： Yoram Karni , Guy Cohen
IPC分类号： H01S3/098 , H01S3/13
CPC分类号： H01S5/4062 , H01S5/065 , H01S5/141 , H01S5/4068 , H01S5/4087
摘要： A laser resonator cavity is presented. The laser resonator cavity comprises an optical manipulator of different longitudinal modes propagating along different optical paths. The optical manipulator is configured for adjusting a difference in optical lengths of the different optical paths thereby adjusting a frequency spacing between the different longitudinal.
摘要翻译：提出了一种激光谐振腔。激光谐振腔包括沿着不同光路传播的不同纵向模的光学操纵器。光学机械手配置用于调节不同光路的光学长度差，从而调节不同纵向之间的频率间隔。

39. 发明授权

US08474061B2 Production scale fabrication method for high resolution AFM tips 失效
标题翻译：高分辨率AFM提示的生产规模制作方法
公开(公告)号：US08474061B2
公开(公告)日：2013-06-25
申请号：US13608396
申请日：2012-09-10
申请人： Guy Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
发明人： Guy Cohen , Mark C. Reuter , Brent A. Wacaser , Maha M. Khayyat
IPC分类号： G01Q60/38 , B82Y40/00
CPC分类号： G01Q70/12 , G01Q60/38
摘要： A method of fabricating high resolution atomic force microscopy (AFM) tips including a single semiconductor nanowire grown at an apex of a semiconductor pyramid of each AFM tip is provided. The semiconductor nanowire that is grown has a controllable diameter and a high aspect ratio, without significant tapering from the tip of the semiconductor nanowire to its base. The method includes providing an AFM probe including a semiconductor cantilever having a semiconductor pyramid extending upward from a surface of said semiconductor cantilever. The semiconductor pyramid has an apex. A patterned oxide layer is formed on the AFM probe. The patterned oxide layer has an opening that exposes the apex of the semiconductor pyramid. A single semiconductor nanowire is grown on the exposed apex of the semiconductor pyramid utilizing a non-oxidized Al seed material as a catalyst for nanowire growth.
摘要翻译：提供了一种制造高分辨率原子力显微镜（AFM）尖端的方法，其包括在每个AFM尖端的半导体金字塔的顶点处生长的单个半导体纳米线。生长的半导体纳米线具有可控直径和高纵横比，而没有从半导体纳米线的尖端到其基底的显着锥形化。该方法包括提供包括半导体悬臂的AFM探针，该半导体悬臂具有从所述半导体悬臂的表面向上延伸的半导体金字塔。半导体金字塔有顶点。在AFM探针上形成图案化的氧化物层。图案化氧化物层具有暴露半导体金字塔的顶点的开口。使用未氧化的Al种子材料作为纳米线生长的催化剂，在半导体金字塔的暴露的顶点上生长单个半导体纳米线。

40. 发明授权

US08445892B2 p-FET with a strained nanowire channel and embedded SiGe source and drain stressors 有权
公开(公告)号：US08445892B2
公开(公告)日：2013-05-21
申请号：US13554065
申请日：2012-07-20
申请人： Guy Cohen , Conal E. Murray , Michael J. Rooks
发明人： Guy Cohen , Conal E. Murray , Michael J. Rooks
IPC分类号： H01L29/775
CPC分类号： H01L29/78696 , H01L29/0673 , H01L29/42392 , H01L29/7848 , H01L29/785
摘要： Techniques for embedding silicon germanium (e-SiGe) source and drain stressors in nanoscale channel-based field effect transistors (FETs) are provided. In one aspect, a method of fabricating a FET includes the following steps. A doped substrate having a dielectric thereon is provided. At least one silicon (Si) nanowire is placed on the dielectric. One or more portions of the nanowire are masked off leaving other portions of the nanowire exposed. Epitaxial germanium (Ge) is grown on the exposed portions of the nanowire. The epitaxial Ge is interdiffused with Si in the nanowire to form SiGe regions embedded in the nanowire that introduce compressive strain in the nanowire. The doped substrate serves as a gate of the FET, the masked off portions of the nanowire serve as channels of the FET and the embedded SiGe regions serve as source and drain regions of the FET.

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