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31. 发明申请

US20100072520A1 Methods of Fabricating Transistors Having Buried P-Type Layers Coupled to the Gate 有权
标题翻译：制造具有埋入P型层的晶体管耦合到栅极的方法
公开(公告)号：US20100072520A1
公开(公告)日：2010-03-25
申请号：US12627743
申请日：2009-11-30
申请人： Saptharishi Sriram , Matt Willis
发明人： Saptharishi Sriram , Matt Willis
IPC分类号： H01L29/812 , H01L21/338
CPC分类号： H01L29/8128 , H01L29/1029 , H01L29/1066 , H01L29/808
摘要： A unit cell of a metal-semiconductor field-effect transistor (MESFET) is provided. The MESFET has a source, a drain and a gate. The gate is between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the gate between the source and the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel layer and electrically coupled to the gate. Related methods are also provided herein.
摘要翻译：提供了一种金属半导体场效应晶体管（MESFET）的晶胞。 MESFET具有源极，漏极和栅极。栅极在源极和漏极之间以及n型导电沟道层之间。在源极和漏极之间的栅极下方提供p型导电区域。 p型导电区域与n型导电沟道层间隔开并电耦合到栅极。本文还提供了相关方法。

32. 发明申请

US20080197382A1 Metal-semiconductor field effect transistors (MESFETs) having self-aligned structures and methods of fabricating the same 有权
标题翻译：具有自对准结构的金属 - 半导体场效应晶体管（MESFET）及其制造方法
公开(公告)号：US20080197382A1
公开(公告)日：2008-08-21
申请号：US11706762
申请日：2007-02-15
申请人： Saptharishi Sriram , Jason Henning , Keith Wieber
发明人： Saptharishi Sriram , Jason Henning , Keith Wieber
IPC分类号： H01L29/12 , H01L21/338 , H01L29/80
CPC分类号： H01L29/1608 , H01L29/1029 , H01L29/66068 , H01L29/812
摘要： Metal-semiconductor field-effect transistors (MESFETS) are provided. A MESFET is provided having a source region, a drain region and a gate. The gate is between the source region and the drain region. A p-type conductivity layer is provided beneath the source region, the p-type conductivity layer being self-aligned to the gate. Related methods of fabricating MESFETs are also provided herein.
摘要翻译：提供了金属半导体场效应晶体管（MESFETS）。提供了具有源极区，漏极区和栅极的MESFET。栅极在源极区域和漏极区域之间。 p型导电层设置在源极区域的下方，p型导电层与栅极自对准。本文还提供了制造MESFET的相关方法。

33. 发明授权

US07348612B2 Metal-semiconductor field effect transistors (MESFETs) having drains coupled to the substrate and methods of fabricating the same 有权
标题翻译：具有与衬底耦合的漏极的金属半导体场效应晶体管（MESFET）及其制造方法
公开(公告)号：US07348612B2
公开(公告)日：2008-03-25
申请号：US10977054
申请日：2004-10-29
申请人： Saptharishi Sriram , Scott Allen
发明人： Saptharishi Sriram , Scott Allen
IPC分类号： H01L31/112
CPC分类号： H01L29/66848 , H01L29/1075 , H01L29/1608 , H01L29/4175 , H01L29/8128
摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a MESFET having a source region, a drain region and a gate contact. The gate contact is disposed between the source region and the drain region. The drain region is electrically coupled to the substrate through a contact via hole to the substrate. Related methods of fabricating MESFETs are also provided herein.
摘要翻译：本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括具有源极区，漏极区和栅极接触的MESFET。栅极触点设置在源极区域和漏极区域之间。漏极区域通过接触通孔电耦合到衬底到衬底。本文还提供了制造MESFET的相关方法。

34. 发明授权

US07326962B2 Transistors having buried N-type and P-type regions beneath the source region and methods of fabricating the same 有权
标题翻译：晶体管在源极区域下方埋有N型和P型区域及其制造方法
公开(公告)号：US07326962B2
公开(公告)日：2008-02-05
申请号：US11012553
申请日：2004-12-15
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L29/04
CPC分类号： H01L29/0619 , H01L29/1608 , H01L29/2003 , H01L29/41766 , H01L29/8128
摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source. An n-type conductivity region is provided on the p-type conductivity region beneath the source region and extending toward the drain region without extending beyond the end of the p-type conductivity region. Related methods of fabricating MESFETS are also provided.
摘要翻译：本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括源极，漏极和栅极。栅极设置在源极和漏极之间以及n型导电沟道层上。在源极下方提供p型导电区域，并且具有朝向漏极延伸的端部。 p型导电区域与n型导电沟道区域间隔开并且电耦合到源极。在源极区域下方的p型导电性区域上设置n型导电性区域，并且朝向漏极区域延伸，而不延伸超过p型导电性区域的端部。还提供了制造MESFETS的相关方法。

35. 发明授权

US07297580B2 Methods of fabricating transistors having buried p-type layers beneath the source region 有权
标题翻译：制造在源极区下面埋有p型层的晶体管的方法
公开(公告)号：US07297580B2
公开(公告)日：2007-11-20
申请号：US11142551
申请日：2005-06-01
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L21/338
CPC分类号： H01L29/66856 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/812 , H01L29/8128
摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.
摘要翻译：本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括源极，漏极和栅极。栅极设置在源极和漏极之间以及n型导电沟道层上。在源极下方提供p型导电区域，并且具有朝向漏极延伸的端部。 p型导电区域与n型导电沟道区域间隔开并且电耦合到源极。

36. 发明申请

US20060284261A1 Semiconductor devices having varying electrode widths to provide non-uniform gate pitches and related methods 有权
标题翻译：具有变化的电极宽度以提供不均匀栅极间距的半导体器件和相关方法
公开(公告)号：US20060284261A1
公开(公告)日：2006-12-21
申请号：US11157356
申请日：2005-06-21
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L29/76
CPC分类号： H01L29/41758 , H01L29/42316
摘要： Semiconductor devices including a plurality of unit cells connected in parallel are provided. Each of the unit cells have a first electrode, a second electrode and a gate finger. One of the first electrodes at a center of the semiconductor device has a first width and one of the first electrodes at a periphery of the semiconductor device has a second width, smaller than the first width. The second electrodes have a substantially constant width such that a pitch between the gate fingers is non-uniform. Related methods are also provided.
摘要翻译：提供包括并联连接的多个单元的半导体装置。每个单元电池具有第一电极，第二电极和栅极指。在半导体器件的中心处的第一电极之一具有第一宽度，半导体器件的周边处的第一电极中的一个具有小于第一宽度的第二宽度。第二电极具有基本恒定的宽度，使得栅极指之间的间距不均匀。还提供了相关方法。

37. 发明授权

US06956239B2 Transistors having buried p-type layers beneath the source region 有权
标题翻译：晶体管具有在源极区下面的p型层
公开(公告)号：US06956239B2
公开(公告)日：2005-10-18
申请号：US10304272
申请日：2002-11-26
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L21/04 , H01L21/338 , H01L29/20 , H01L29/24 , H01L29/812 , H01L31/0312
CPC分类号： H01L29/66856 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/812 , H01L29/8128
摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.
摘要翻译：本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括源极，漏极和栅极。栅极设置在源极和漏极之间以及n型导电沟道层上。在源极下方提供p型导电区域，并且具有朝向漏极延伸的端部。 p型导电区域与n型导电沟道区域间隔开并且电耦合到源极。

38. 发明申请

US20050224809A1 Transistors having buried p-type layers beneath the source region and methods of fabricating the same 有权
标题翻译：具有在源极区下面的p型层的晶体管及其制造方法
公开(公告)号：US20050224809A1
公开(公告)日：2005-10-13
申请号：US11142551
申请日：2005-06-01
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L21/04 , H01L21/338 , H01L29/20 , H01L29/24 , H01L29/812 , H01L29/15
CPC分类号： H01L29/66856 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/812 , H01L29/8128
摘要： The present invention provides a unit cell of a metal-semiconductor field-effect transistor (MESFET). The unit cell of the MESFET includes a source, a drain and a gate. The gate is disposed between the source and the drain and on an n-type conductivity channel layer. A p-type conductivity region is provided beneath the source and has an end that extends towards the drain. The p-type conductivity region is spaced apart from the n-type conductivity channel region and is electrically coupled to the source.
摘要翻译：本发明提供了一种金属半导体场效应晶体管（MESFET）的单元。 MESFET的单元包括源极，漏极和栅极。栅极设置在源极和漏极之间以及n型导电沟道层上。在源极下方提供p型导电区域，并且具有朝向漏极延伸的端部。 p型导电区域与n型导电沟道区域间隔开并且电耦合到源极。

39. 发明授权

US5821576A Silicon carbide power field effect transistor 失效
标题翻译：碳化硅功率场效应晶体管
公开(公告)号：US5821576A
公开(公告)日：1998-10-13
申请号：US745975
申请日：1996-11-08
申请人： Saptharishi Sriram
发明人： Saptharishi Sriram
IPC分类号： H01L21/04 , H01L29/20 , H01L29/24 , H01L29/812 , H01L29/80
CPC分类号： H01L29/1608 , H01L21/045 , H01L29/20 , H01L29/8128
摘要： The invention provides for a field effect transistor (FET) which includes a substrate and a buffer layer formed upon the substrate and an active layer formed upon the buffer layer. The active layer includes a gate region, drain region and source region. In addition, a channel region is formed in the active layer intermediate the source region and drain region. The channel region includes a first portion of reduced thickness adjacent the drain region. The active layer may include a recess adjacent the drain region to provide the thin channel region. Preferably, the thickness of the first portion of the channel region is equal to the undepleted channel thickness within the second portion of the channel region adjacent the first portion. The substrate, buffer layer, active layer, and degenerate layers are preferably fabricated of silicon carbide or gallium nitride. Further, the FET preferably includes a p type buffer, n type active layer, and n+ degenerate layers. The FET may also include a surface-effect-suppressive layer which preferably covers portions of the active layer and the degenerate layers.
摘要翻译：本发明提供一种场效应晶体管（FET），其包括衬底和形成在衬底上的缓冲层和形成在缓冲层上的有源层。有源层包括栅极区，漏极区和源极区。此外，在源极区和漏极区中间的有源层中形成沟道区。沟道区域包括邻近漏极区域的厚度减小的第一部分。有源层可以包括邻近漏极区的凹部以提供薄沟道区。优选地，沟道区域的第一部分的厚度等于与第一部分相邻的沟道区域的第二部分内的未剥离通道厚度。衬底，缓冲层，有源层和简并层优选由碳化硅或氮化镓制成。此外，FET优选包括p型缓冲器，n型有源层和n +简并层。 FET还可以包括优选覆盖有源层和简并层的部分的表面效应抑制层。

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