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31. 发明授权

US06656748B2 FeRAM capacitor post stack etch clean/repair 有权
标题翻译： FeRAM电容器堆栈蚀刻清洁/修复
公开(公告)号：US06656748B2
公开(公告)日：2003-12-02
申请号：US10125662
申请日：2002-04-18
申请人： Lindsey H. Hall , Scott R. Summerfelt
发明人： Lindsey H. Hall , Scott R. Summerfelt
IPC分类号： H01L2100
CPC分类号： H01L21/31122 , H01L21/31691 , H01L21/32136 , H01L27/105 , H01L27/11502 , H01L27/11507 , H01L27/11509 , H01L28/55
摘要： The present invention is directed to a method of forming an FeRAM integrated circuit, which includes performing a capacitor stack etch to define the FeRAM capacitor. The method comprises etching a PZT ferroelectric layer with a high temperature BCl3 etch which provides substantial selectivity with respect to the hard mask. Alternatively, the PZT ferroelectric layer is etch using a low temperature fluorine component etch chemistry such as CHF3 to provide a non-vertical PZT sidewall profile. Such a profile prevents conductive material associated with a subsequent bottom electrode layer etch from depositing on the PZT sidewall, thereby preventing leakage or a “shorting out” of the resulting FeRAM capacitor.
摘要翻译：本发明涉及形成FeRAM集成电路的方法，其包括执行电容器堆叠蚀刻以限定FeRAM电容器。该方法包括用提供相对于硬掩模的实质选择性的高温BCl3蚀刻来蚀刻PZT铁电层。或者，PZT铁电层是使用诸如CHF 3的低温氟成分蚀刻化学品进行蚀刻以提供非垂直PZT侧壁轮廓。这种轮廓防止与随后的底部电极层蚀刻相关联的导电材料沉积在PZT侧壁上，从而防止所得FeRAM电容器的泄漏或“短路”。

32. 发明授权

US06593638B1 Lightly donor doped electrodes for high-dielectric-constant materials 失效
标题翻译：用于高介电常数材料的轻掺杂掺杂电极
公开(公告)号：US06593638B1
公开(公告)日：2003-07-15
申请号：US08477957
申请日：1995-06-07
申请人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
发明人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
IPC分类号： H01L2900
CPC分类号： H01G4/008 , H01L21/31691 , H01L27/11502 , H01L28/56 , Y10S257/917 , Y10T29/43 , Y10T29/435
摘要： A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions. The lightly donor doped perovskite can be deposited and etched by effectively the same techniques that are developed for the high-dielectric-constant material. The same equipment may used to deposit and etch both the perovskite electrode and the dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.
摘要翻译：本发明的优选实施方案包括导电轻掺杂的钙钛矿层（例如轻掺杂的La掺杂的BST 34）和覆盖导电的轻掺杂的钙钛矿层的高介电常数材料层（例如未掺杂的BST 36）。导电轻掺杂的钙钛矿层提供了与高介电常数材料层基本上化学和结构稳定的电连接。掺杂的轻掺杂钙钛矿的电阻通常比未掺杂，受体掺杂或重掺杂的HDC材料具有更低的电阻。导电（或电阻）材料的施主掺杂量通常取决于工艺条件（例如温度，气氛，晶粒尺寸，膜厚度和组成）。如果钙钛矿暴露于还原条件下，该电阻率可以进一步降低。通过有效地为高介电常数材料开发的相同技术，可以沉积和蚀刻轻掺杂的钙钛矿。相同的设备可用于沉积和蚀刻钙钛矿电极和电介质。这些结构也可以用于多层电容器和其他薄膜铁电体器件，例如热电材料，非易失性存储器，薄膜压电和薄膜电光氧化物。

33. 发明授权

US06362499B1 Ferroelectric transistors using thin film semiconductor gate electrodes 有权
标题翻译：使用薄膜半导体栅电极的铁电晶体管
公开(公告)号：US06362499B1
公开(公告)日：2002-03-26
申请号：US09645158
申请日：2000-08-24
申请人： Theodore S. Moise , Scott R. Summerfelt
发明人： Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L2976
CPC分类号： G11C29/44 , G11C11/223 , G11C2029/1208 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric structure on an integrated circuit and methods of making and using the same are disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.
摘要翻译：公开了集成电路中的铁电结构及其制造和使用的方法，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

34. 发明授权

US06319542B1 Lightly donor doped electrodes for high-dielectric-constant materials 失效
标题翻译：用于高介电常数材料的轻掺杂掺杂电极
公开(公告)号：US06319542B1
公开(公告)日：2001-11-20
申请号：US08451853
申请日：1995-05-26
申请人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
发明人： Scott R. Summerfelt , Howard R. Beratan , Bruce Gnade
IPC分类号： B05D512
CPC分类号： H01G4/008 , H01L21/31691 , H01L27/11502 , H01L28/56 , Y10S257/917 , Y10T29/43 , Y10T29/435
摘要： A preferred embodiment of this invention comprises a conductive lightly donor doped perovskite layer (e.g. lightly La doped BST 34), and a high-dielectric-constant material layer (e.g. undoped BST 36) overlaying the conductive lightly donor doped perovskite layer. The conductive lightly donor doped perovskite layer provides a substantially chemically and structurally stable electrical connection to the high-dielectric-constant material layer. A lightly donor doped perovskite generally has much less resistance than undoped, acceptor doped, or heavily donor doped HDC materials. The amount of donor doping to make the material conductive (or resistive) is normally dependent on the process conditions (e.g. temperature, atmosphere, grain size, film thickness and composition). This resistivity may be further decreased if the perovskite is exposed to reducing conditions. The lightly donor doped perovskite can be deposited and etched by effectively the same techniques that are developed for the high-dielectric-constant material. The same equipment may used to deposit and etch both the perovskite electrode and the dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.
摘要翻译：本发明的优选实施方案包括导电轻掺杂的钙钛矿层（例如轻掺杂的La掺杂的BST 34）和覆盖导电的轻掺杂的钙钛矿层的高介电常数材料层（例如未掺杂的BST 36）。导电轻掺杂的钙钛矿层提供了与高介电常数材料层基本上化学和结构稳定的电连接。掺杂的轻掺杂钙钛矿的电阻通常比未掺杂，受体掺杂或重掺杂的HDC材料具有更低的电阻。导电（或电阻）材料的施主掺杂量通常取决于工艺条件（例如温度，气氛，晶粒尺寸，膜厚度和组成）。如果钙钛矿暴露于还原条件下，该电阻率可以进一步降低。通过有效地为高介电常数材料开发的相同技术，可以沉积和蚀刻轻掺杂的钙钛矿。相同的设备可用于沉积和蚀刻钙钛矿电极和电介质。这些结构也可以用于多层电容器和其他薄膜铁电体器件，例如热电材料，非易失性存储器，薄膜压电和薄膜电光氧化物。

35. 发明授权

US06287903B1 Structure and method for a large-permittivity dielectric using a germanium layer 有权
标题翻译：使用锗层的大介电常数电介质的结构和方法
公开(公告)号：US06287903B1
公开(公告)日：2001-09-11
申请号：US09217337
申请日：1998-12-21
申请人： Yasutoshi Okuno , Scott R. Summerfelt
发明人： Yasutoshi Okuno , Scott R. Summerfelt
IPC分类号： H01L21336
CPC分类号： H01L21/28185 , H01L21/02381 , H01L21/02395 , H01L21/0245 , H01L21/02532 , H01L21/0262 , H01L21/28194 , H01L21/28255 , H01L21/28264 , H01L29/1054 , H01L29/513 , H01L29/517 , H01L29/518 , H01L29/66477 , H01L29/78391 , H01L29/808
摘要： A structure for, and method of forming, a metal-insulator-semiconductor field-effect transistor in an integrated circuit is disclosed. The disclosed method comprises forming a germanium layer 52 on a semiconductor substrate (e.g. silicon 20), depositing a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) on the germanium layer, and forming a gate electrode (e.g., titanium nitride 60) on the gate dielectric. The method may comprise forming source and drain regions 64 in the substrate on either side of the gate dielectric. The germanium layer, which is preferably epitaxially grown, generally prevents formation of a low dielectric constant layer between the gate dielectric and the semiconductor substrate. The disclosed structure comprises a germanium layer 52 disposed on a semiconductor substrate (e.g. silicon 20), a large-permittivity gate dielectric (e.g. tantalum pentoxide 56) disposed on the germanium layer, and a gate electrode (e.g., titanium nitride 60) disposed on the gate dielectric. The structure may comprise source and drain regions 64 disposed in the substrate on either side of the gate dielectric. A GexSi1-x buffer layer 58 may be formed between the semiconductor substrate and the germanium layer, with x transitioning from about 0 near the substrate to about 1 near the germanium layer. The large-permittivity gate dielectric may be either a moderate-dielectric constant oxide or a high-dielectric constant oxide.
摘要翻译：公开了一种集成电路中的金属 - 绝缘体半导体场效应晶体管的结构及其形成方法。所公开的方法包括在半导体衬底（例如硅20）上形成锗层52，在锗层上沉积大电容率栅极电介质（例如五氧化二钽56），以及在锗层上形成栅电极（例如，氮化钛60）栅电介质。该方法可以包括在栅极电介质的任一侧上的衬底中形成源区和漏区64。优选外延生长的锗层通常防止在栅极电介质和半导体衬底之间形成低介电常数层。所公开的结构包括设置在半导体衬底（例如硅20）上的锗层52，设置在锗层上的大电容率栅极电介质（例如五氧化二钽56）和设置在锗层上的栅极（例如，氮化钛60）栅电介质。该结构可以包括在栅极电介质的任一侧上设置在衬底中的源极和漏极区域64。可以在半导体衬底和锗层之间形成GexSi1-x缓冲层58，其中在衬底附近从约0转移到接近锗层的约1。大电容率栅极电介质可以是中等介电常数氧化物或高介电常数氧化物。

36. 发明授权

US06225655B1 Ferroelectric transistors using thin film semiconductor gate electrodes 失效
标题翻译：使用薄膜半导体栅电极的铁电晶体管
公开(公告)号：US06225655B1
公开(公告)日：2001-05-01
申请号：US08953947
申请日：1997-10-20
申请人： Theodore S. Moise , Scott R. Summerfelt
发明人： Theodore S. Moise , Scott R. Summerfelt
IPC分类号： H01L2976
CPC分类号： G11C29/44 , G11C11/223 , G11C2029/1208 , H01L21/28291 , H01L29/78391
摘要： A ferroelectric structure on an integrated circuit is disclosed, which may be used, for instance, in a high-speed, non-volatile, non-destructive readout random-access memory device. Generally, the ferroelectric structure combines a thin film ferroelectric variable resistor and a substrate (e.g. silicon) transistor, using a semiconducting film which is common to both. A field effect transistor 26 integrated into substrate 30 has a gate oxide 36 and a semiconducting gate electrode 38 with electrical connections at a first end 44 and a second end 46. Overlying gate electrode 38 is a ferroelectric thin film 40 and a conductive electrode 42. The polarization of ferroelectric thin film 40 is set by applying an appropriate voltage between gate electrode 38 and conductive electrode 42. The polarization of ferroelectric thin film 40 may be subsequently determined by applying a read voltage to 42 and 44, thus causing a voltage V2 to appear at 46 which is determined by the polarization of the ferroelectric variable resistor formed by 38 and 40. Since 38 also forms the gate electrode for field effect transistor 26, the magnitude of V2 affects the magnitude of current I2. Thus I2 is effectively an amplified signal related to the ferroelectric variable resistance which may be read without perturbing the polarization of ferroelectric thin film 40.
摘要翻译：公开了集成电路中的铁电结构，其可以用于例如高速，非易失性，非破坏性读出随机存取存储器件中。通常，铁电结构使用两者共同的半导体膜组合薄膜铁电可变电阻器和衬底（例如硅）晶体管。集成到基板30中的场效应晶体管26具有在第一端44和第二端46具有电连接的栅极氧化物36和半导体栅电极38.叠层栅电极38是铁电薄膜40和导电电极42。通过在栅电极38和导电电极42之间施加适当的电压来设定铁电薄膜40的极化。随后可以通过将读电压施加到42和44来确定铁电薄膜40的极化，从而使电压V2 出现在46处，其由38和40形成的铁电可变电阻器的极化决定。由于38还形成场效应晶体管26的栅电极，因此V2的大小影响电流I2的大小。因此，I2实际上是与铁电可变电阻相关的放大信号，其可以在不扰乱铁电薄膜40的极化的情况下读取。

37. 发明授权

US06177351B1 Method and structure for etching a thin film perovskite layer 有权
标题翻译：蚀刻薄膜钙钛矿层的方法和结构
公开(公告)号：US06177351B1
公开(公告)日：2001-01-23
申请号：US09218936
申请日：1998-12-22
申请人： Howard R. Beratan , Scott R. Summerfelt , James F. Belcher
发明人： Howard R. Beratan , Scott R. Summerfelt , James F. Belcher
IPC分类号： H01L21302
CPC分类号： H01L21/76831 , H01L21/0332 , H01L21/31122 , H01L21/76802 , H01L21/76843 , H01L21/76849 , H01L21/76855 , H01L21/7687 , H01L21/76877 , H01L27/10814 , H01L27/10882 , H01L27/10894 , H01L28/55
摘要： A method and structure for etching a thin film perovskite layer (e.g., barium strontium titanate 836) overlying a second material without substantially etching the second material. The method comprises forming a substantially-silicon-free dielectric etchstop layer (e.g., aluminum nitride 858) on a second dielectric layer comprising silicon (e.g., silicon dioxide 818), depositing the perovskite layer over the etchstop layer, forming a mask layer (e.g., photoresist 842) over the perovsklte layer, patterning and removing portions of the mask layer to form a desired pattern, and etching portions of the perovskite layer not covered by the mask layer, whereby the etching stops on the etchstop layer. The structure comprises a substantially-silicon-free dielectric etchstop layer overlying a second dielectric layer comprising silicon, and a perovskite layer having a desired pattern and comprising an etched side overlying a substantially unetched portion of the etchstop layer.
摘要翻译：用于蚀刻覆盖第二材料而不实质蚀刻第二材料的薄膜钙钛矿层（例如，钛酸钡锶836）的方法和结构。该方法包括在包括硅的第二介电层（例如，二氧化硅818）上形成基本上无硅的电介质蚀刻阻挡层（例如，氮化铝858），在蚀刻阻挡层上沉积钙钛矿层，形成掩模层（例如，，光致抗蚀剂842），图案化和去除掩模层的部分以形成期望的图案，以及蚀刻未被掩模层覆盖的钙钛矿层的部分，由此在蚀刻停止层上停止蚀刻。该结构包括覆盖包括硅的第二介电层的基本上无硅的电介质蚀刻阻挡层，以及具有期望图案的钙钛矿层，并且包括覆盖蚀刻阻挡层的基本未蚀刻部分的蚀刻侧。

38. 发明授权

US6153490A Method for forming integrated circuit capacitor and memory 失效
公开(公告)号：US6153490A
公开(公告)日：2000-11-28
申请号：US105738
申请日：1998-06-26
申请人： Guoqiang Xing , Scott R. Summerfelt , Rajesh Khamankar
发明人： Guoqiang Xing , Scott R. Summerfelt , Rajesh Khamankar
IPC分类号： H01L21/02 , H01L21/3213 , H01L21/8242 , H01L21/20 , H01L21/00 , H01L21/302 , H01L21/44
CPC分类号： H01L27/10852 , H01L21/32136 , H01L21/32139 , H01L28/60 , H01L28/55
摘要： A method for etching a feature in a platinum layer 834 overlying a second material 818 without substantially etching the second material. The method includes the the steps of: forming an adhesion-promoting layer 824 between the platinum layer and the second material; forming a hardmask layer 829 over the platinum layer; patterning and etching the hardmask layer in accordance with desired dimensions of the feature; and etching portions of the platinum layer not covered by the hardmask layer 832, the etching stopping on the adhesion-promoting layer. In further embodiments the adhesion-promoting and hardmask layers are Ti--Al--N including at least 1% of aluminum.

39. 发明授权

US5912486A Pb/Bi-containing high-dielectric constant oxides using a non-Pb/Bi-containing perovskite as a buffer layer 失效
标题翻译：含有Pb / Bi的高介电常数氧化物，使用非Pb / Bi的钙钛矿作为缓冲层
公开(公告)号：US5912486A
公开(公告)日：1999-06-15
申请号：US842863
申请日：1997-04-17
申请人： Scott R. Summerfelt
发明人： Scott R. Summerfelt
IPC分类号： C23C14/08 , H01L21/02 , H01L21/28 , H01L21/314 , H01L21/316 , H01L21/8242 , H01L27/108 , H01L29/51 , H05K1/03
CPC分类号： H01L21/28185 , H01L21/02197 , H01L21/02304 , H01L21/28158 , H01L21/28167 , H01L21/28194 , H01L21/314 , H01L28/56 , H01L29/513 , H01L29/517 , Y10S148/014 , Y10S148/118 , Y10S438/967
摘要： This is a method for fabricating a structure useful in semiconductor circuitry. The method comprises: growing a buffer layer of non-Pb/Bi-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate; and depositing a Pb/Bi-containing high-dielectric constant oxide on the buffer layer. Alternately this may be a structure useful in semiconductor circuitry, comprising: a buffer layer 26 of non-lead-containing high-dielectric constant oxide layer directly or indirectly on a semiconductor substrate 10; and a lead-containing high-dielectric constant oxide 28 on the buffer layer. Preferably a germanium layer 12 is epitaxially grown on the semiconductor substrate and the buffer layer is grown on the germanium layer. When the substrate is silicon, the non-Pb/Bi-containing high-dielectric constant oxide layer is preferably less than about 10 nm thick. A second non-Pb/Bi-containing high-dielectric constant oxide layer 30 may be grown on top of the Pb/Bi-containing high-dielectric constant oxide and a conducting layer (top electrode 32) may also be grown on the second non-Pb/Bi-containing high-dielectric constant oxide layer.
摘要翻译：这是用于制造在半导体电路中有用的结构的方法。该方法包括：在半导体衬底上直接或间接生长非Pb / Bi的高介电常数氧化物层的缓冲层; 以及在所述缓冲层上沉积含Pb / Bi的高介电常数氧化物。或者，这可以是在半导体电路中有用的结构，其包括：直接或间接地在半导体衬底10上的非含铅高介电常数氧化物层的缓冲层26; 和在缓冲层上的含铅高介电常数氧化物28。优选地，在半导体衬底上外延生长锗层12，并且在锗层上生长缓冲层。当衬底是硅时，非Pb / Bi的高介电常数氧化物层的厚度优选小于约10nm。可以在含Pb / Bi的高介电常数氧化物的顶部上生长第二非Pb / Bi的高介电常数氧化物层30，并且还可以在第二非绝缘材料上生长导电层（顶电极32） -Pb / Bi高介电常数氧化物层。

40. 发明授权

US5781404A Electrode interface for high-dielectric-constant materials 失效
公开(公告)号：US5781404A
公开(公告)日：1998-07-14
申请号：US485856
申请日：1995-06-07
申请人： Scott R. Summerfelt , Howard Roy Beratan
发明人： Scott R. Summerfelt , Howard Roy Beratan
IPC分类号： H01G4/33 , H01G4/30 , H01G7/06 , H01L21/02 , H01L21/822 , H01L27/04 , H01L27/115 , H01G4/10
CPC分类号： H01L27/11502 , H01G4/306 , H01G7/06 , H01L28/56
摘要： A preferred embodiment of this invention comprises a first thin dielectric buffer layer of a first leakage-current-density material (e.g. strontium titanate 32) with a first moderate-dielectric-constant, a high-dielectric-constant layer of a second leakage-current-density material (e.g. barium strontium titanate 34) overlaying the first thin dielectric buffer layer, and a second thin dielectric buffer layer of a third leakage-current-density material (e.g. strontium titanate 36) with a second moderate-dielectric-constant overlaying the high-dielectric-constant layer, wherein the first and third leakage-current-density materials have substantially lower leakage-current-densities than the second leakage-current-density material. The first and second thin moderate-dielectric-constant buffer layers (e.g. strontium titanate 32, 36) substantially limit the leakage-current-density of the structure, with only modest degradation of the dielectric constant of the structure. The possibly lower dielectric constant of the structure is generally compensated for by the reduced leakage current of the structure. The additional layers generally require only minor modifications of existing processes, since the same processes that are used for the high-dielectric-constant oxide can generally be used for the low leakage-current-density dielectric. These structures may also be used for multilayer capacitors and other thin-film ferroelectric devices such as pyroelectric materials, non-volatile memories, thin-film piezoelectric and thin-film electro-optic oxides.

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