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31. 发明申请

US20120039106A1 Programmable Memory Cell with Shiftable Threshold Voltage Transistor 有权
标题翻译：具有可移位阈值电压晶体管的可编程存储单元
公开(公告)号：US20120039106A1
公开(公告)日：2012-02-16
申请号：US13283418
申请日：2011-10-27
申请人： Frank Hui , Xiangdong Chen , Wei Xia
发明人： Frank Hui , Xiangdong Chen , Wei Xia
IPC分类号： G11C17/08
CPC分类号： G11C17/16 , G11C17/18 , H01L27/115
摘要： According to one exemplary embodiment, a one-time programmable memory cell includes an access transistor coupled to a shiftable threshold voltage transistor between a bitline and a ground, where the access transistor has a gate coupled to a wordline. The shiftable threshold voltage transistor has a drain and a gate shorted together. A programming operation causes a permanent shift in a threshold voltage of the shiftable threshold voltage transistor to occur in response to a programming voltage on the bitline and the wordline. In one embodiment, the access transistor is an NFET while the shiftable threshold voltage transistor is a PFET. In another embodiment, the access transistor is an NFET and the shiftable threshold voltage transistor is also an NFET. The programming voltage can cause an absolute value of the threshold voltage to permanently increase by at least 50.0 millivolts.
摘要翻译：根据一个示例性实施例，一次性可编程存储器单元包括耦合到位线和地之间的可移位阈值电压晶体管的存取晶体管，其中存取晶体管具有耦合到字线的栅极。可移位阈值电压晶体管具有漏极和栅极短路在一起。编程操作导致响应于位线和字线上的编程电压而发生可移位阈值电压晶体管的阈值电压的永久偏移。在一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管是PFET。在另一个实施例中，存取晶体管是NFET，而可移位阈值电压晶体管也是NFET。编程电压可导致阈值电压的绝对值永久增加至少50.0毫伏。

32. 发明授权

US08089118B2 Method for selective gate halo implantation in a semiconductor die and related structure 有权
标题翻译：半导体晶片中选择性栅晕注入的方法及相关结构
公开(公告)号：US08089118B2
公开(公告)日：2012-01-03
申请号：US12456065
申请日：2009-06-10
申请人： Xiangdong Chen , Henry Kuo-Shun Chen , Kent Charles Oertle , Jennifer Chiao
发明人： Xiangdong Chen , Henry Kuo-Shun Chen , Kent Charles Oertle , Jennifer Chiao
IPC分类号： H01L29/788 , H01L29/792 , H01L29/76 , H01L29/94 , H01L31/062
CPC分类号： H01L29/66575 , H01L21/26586 , H01L29/1045 , H01L29/66537 , H01L29/78
摘要： According to one embodiment, a method for selective gate halo implantation includes forming at least one gate having a first orientation and at least one gate having a second orientation over a substrate. The method further includes performing a halo implant over the substrate. The first orientation allows a halo implanted area to be formed under the at least one gate having the first orientation and the second orientation prevents a halo implanted area from forming under the at least one gate having the second orientation. The halo implant is performed without forming a mask over the at least one gate having the first orientation or the at least one gate having the second orientation. The at least one gate having the first orientation can be used in a low voltage region of a substrate, while the at least one gate having the second orientation can be used in a high voltage region.
摘要翻译：根据一个实施例，用于选择性栅极晕晕注入的方法包括在衬底上形成具有第一取向的至少一个栅极和具有第二取向的至少一个栅极。该方法还包括在衬底上执行晕轮植入。第一取向允许在具有第一取向的至少一个栅极下方形成光晕注入区域，并且第二取向防止在具有第二取向的至少一个栅极下形成光晕注入区域。在没有在具有第一取向的至少一个栅极或具有第二取向的至少一个栅极上形成掩模的情况下执行光晕注入。具有第一取向的至少一个栅极可用于衬底的低电压区域，而具有第二取向的至少一个栅极可用于高电压区域。

33. 发明申请

US20110175170A1 STRUCTURE AND METHOD FOR MAKING LOW LEAKAGE AND LOW MISMATCH NMOSFET 失效
标题翻译：用于制造低漏电和低失真的NMOSFET的结构和方法
公开(公告)号：US20110175170A1
公开(公告)日：2011-07-21
申请号：US12691183
申请日：2010-01-21
申请人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
发明人： Xinlin Wang , Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/66 , H01L21/8238
CPC分类号： H01L27/092 , H01L21/823462 , H01L21/823468 , H01L21/823857 , H01L21/823864 , H01L27/11 , H01L27/1104
摘要： An improved SRAM and fabrication method are disclosed. The method comprises use of a nitride layer to encapsulate PFETs and logic NFETs, protecting the gates of those devices from oxygen exposure. NFETs that are used in the SRAM cells are exposed to oxygen during the anneal process, which alters the effective work function of the gate metal, such that the threshold voltage is increased, without the need for increasing the dopant concentration, which can adversely affect issues such as mismatch due to random dopant fluctuation, GIDL and junction leakage.
摘要翻译：公开了一种改进的SRAM和制造方法。该方法包括使用氮化物层来封装PFET和逻辑NFET，保护这些器件的栅极免受氧气暴露。用于SRAM单元中的NFET在退火过程中暴露于氧气，这改变了栅极金属的有效功函数，使得阈值电压增加，而不需要增加掺杂剂浓度，这可能不利地影响问题例如由于随机掺杂剂波动，GIDL和结泄漏引起的失配。

34. 发明授权

US07935993B2 Semiconductor device structure having enhanced performance FET device 有权
标题翻译：具有增强型FET器件的半导体器件结构
公开(公告)号：US07935993B2
公开(公告)日：2011-05-03
申请号：US12643482
申请日：2009-12-21
申请人： Xiangdong Chen , Haining S. Yang
发明人： Xiangdong Chen , Haining S. Yang
IPC分类号： H01L29/76
CPC分类号： H01L21/823807 , H01L29/6653 , H01L29/6656 , H01L29/6659 , H01L29/7833 , H01L29/7843
摘要： A method for making a semiconductor device structure, includes: providing a substrate; forming on the substrate: a first layer below and second layers on a gate with spacers, source and drain regions adjacent to the gate, silicides on the gate and source and drain regions; disposing a stress layer over the structure resulting from the forming step; disposing an insulating layer over the stress layer; removing portions of the insulating layer to expose a top surface of the stress layer; removing the top surface and other portions of the stress layer and portions of the spacers to form a trench, and then disposing a suitable stress material into the trench.
摘要翻译：一种制造半导体器件结构的方法，包括：提供衬底; 在衬底上形成：在栅极上的第一层和栅极上的第二层，具有间隔物，与栅极相邻的源极和漏极区域，栅极上的硅化物和源极和漏极区域; 在由成形步骤导致的结构上设置应力层; 在应力层上设置绝缘层; 去除绝缘层的部分以暴露应力层的顶表面; 去除应力层的顶表面和其它部分和间隔物的部分以形成沟槽，然后将合适的应力材料设置到沟槽中。

35. 发明申请

US20110049620A1 Method for fabricating a MOS transistor with source/well heterojunction and related structure 有权
标题翻译：用于制造具有源/阱异质结及相关结构的MOS晶体管的方法
公开(公告)号：US20110049620A1
公开(公告)日：2011-03-03
申请号：US12583977
申请日：2009-08-28
申请人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
发明人： Xiangdong Chen , Bruce Chih-Chieh Shen , Henry Kuo-Shun Chen
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/7816 , H01L29/0653 , H01L29/0856 , H01L29/086 , H01L29/165 , H01L29/267 , H01L29/6656 , H01L29/66689 , H01L29/7848
摘要： According to an exemplary embodiment, a method for fabricating a MOS transistor, such as an LDMOS transistor, includes forming a gate stack over a well. The method further includes forming a recess in the well adjacent to a first sidewall of the gate stack. The method further includes forming a source region in the recess such that a heterojunction is formed between the source region and the well. The method further includes forming a drain region spaced apart from a second sidewall of the gate stack. In one embodiment, the source region can comprise silicon germanium and the well can comprise silicon. In another embodiment, the source region can comprise silicon carbide and the well can comprise silicon.
摘要翻译：根据示例性实施例，用于制造诸如LDMOS晶体管的MOS晶体管的方法包括在阱上形成栅极堆叠。所述方法还包括在所述阱中形成与所述栅极堆叠的第一侧壁相邻的凹部。该方法还包括在凹部中形成源极区域，使得在源区域和阱之间形成异质结。该方法还包括形成与栅极堆叠的第二侧壁间隔开的漏极区域。在一个实施例中，源极区域可以包括硅锗，并且阱可以包括硅。在另一个实施例中，源极区域可以包括碳化硅，阱可以包括硅。

36. 发明授权

US07867839B2 Method to reduce threshold voltage (Vt) in silicon germanium (SiGe), high-k dielectric-metal gate, p-type metal oxide semiconductor field effect transistors 有权
标题翻译：降低硅锗（SiGe），高k电介质金属栅极，p型金属氧化物半导体场效应晶体管中的阈值电压（Vt）的方法
公开(公告)号：US07867839B2
公开(公告)日：2011-01-11
申请号：US12176634
申请日：2008-07-21
申请人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
发明人： Xiangdong Chen , Jong Ho Lee , Weipeng Li , Dae-Gyu Park , Kenneth J. Stein , Voon-Yew Thean
IPC分类号： H01L21/8238
CPC分类号： H01L21/823857 , H01L21/2652 , H01L21/823807 , H01L29/1054
摘要： Disclosed are embodiments of a p-type, silicon germanium (SiGe), high-k dielectric-metal gate, metal oxide semiconductor field effect transistor (PFET) having an optimal threshold voltage (Vt), a complementary metal oxide semiconductor (CMOS) device that includes the PFET and methods of forming both the PFET alone and the CMOS device. The embodiments incorporate negatively charged ions (e.g., fluorine (F), chlorine (Cl), bromine (Br), iodine (I), etc.) into the high-k gate dielectric material of the PFET only so as to selectively adjust the negative Vt of the PFET (i.e., so as to reduce the negative Vt of the PFET).
摘要翻译：公开了具有最佳阈值电压（Vt）的p型硅锗（SiGe），高k电介质金属栅极，金属氧化物半导体场效应晶体管（PFET），互补金属氧化物半导体（CMOS）器件其包括PFET和形成PFET单独和CMOS器件的方法。实施例将带负电荷的离子（例如，氟（F），氯（Cl），溴（Br），碘（I）等）并入PFET的高k栅介质材料中，以便选择性地调节 PFET的负Vt（即，以减小PFET的负Vt）。

37. 发明申请

US20090291540A1 CMOS Process with Optimized PMOS and NMOS Transistor Devices 有权
标题翻译： CMOS工艺与优化的PMOS和NMOS晶体管器件
公开(公告)号：US20090291540A1
公开(公告)日：2009-11-26
申请号：US12125855
申请日：2008-05-22
申请人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
发明人： Da Zhang , Srikanth B. Samavedam , Voon-Yew Thean , Xiangdong Chen
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L21/823807 , H01L21/26506 , H01L21/823814 , H01L29/1054 , H01L29/6659 , H01L29/66636 , H01L29/66651 , H01L29/7843 , H01L29/7848
摘要： A semiconductor process and apparatus includes forming NMOS and PMOS transistors (24, 34) with enhanced hole mobility in the channel region of a transistor by selectively relaxing part of a biaxial-tensile strained semiconductor layer (90) in a PMOS device area (97) to form a relaxed semiconductor layer (91), and then epitaxially growing a bi-axially stressed silicon germanium channel region layer (22) prior to forming the NMOS and PMOS gate structures (26, 36) overlying the channel regions, and then depositing a contact etch stop layer (53-56) over the NMOS and PMOS gate structures. Embedded silicon germanium source/drain regions (84) may also be formed adjacent to the PMOS gate structure (70) to provide an additional uni-axial stress to the bi-axially stressed channel region.
摘要翻译：半导体工艺和装置包括通过选择性地缓解PMOS器件区域（97）中的双轴拉伸应变半导体层（90）的一部分，在晶体管的沟道区域中形成具有增强的空穴迁移率的NMOS和PMOS晶体管（24,34）以形成松弛半导体层（91），然后在形成覆盖沟道区域的NMOS和PMOS栅极结构（26,36）之前外延生长双轴向应力硅锗沟道区域层（22），然后沉积接触蚀刻停止层（53-56）在NMOS和PMOS栅极结构之上。也可以在PMOS栅极结构（70）附近形成嵌入硅锗源极/漏极区（84），以向双轴向应力沟道区提供额外的单轴应力。

38. 发明申请

US20090256173A1 COMPLEMENTARY FIELD EFFECT TRANSISTORS HAVING EMBEDDED SILICON SOURCE AND DRAIN REGIONS 有权
标题翻译：具有嵌入式硅源和漏区的补充场效应晶体管
公开(公告)号：US20090256173A1
公开(公告)日：2009-10-15
申请号：US12103301
申请日：2008-04-15
申请人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
发明人： Xiangdong Chen , Thomas W. Dyer , Haining S. Yang
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/8258 , H01L29/1054 , H01L29/165 , H01L29/66636 , H01L29/7848
摘要： A method is provided of fabricating complementary stressed semiconductor devices, e.g., an NFET having a tensile stressed channel and a PFET having a compressive stressed channel. In such method, a first semiconductor region having a lattice constant larger than silicon can be epitaxially grown on an underlying semiconductor region of a substrate. The first semiconductor region can be grown laterally adjacent to a second semiconductor region which has a lattice constant smaller than that of silicon. Layers consisting essentially of silicon can be grown epitaxially onto exposed major surfaces of the first and second semiconductor regions after which gates can be formed which overlie the epitaxially grown silicon layers. Portions of the first and second semiconductor regions adjacent to the gates can be removed to form recesses. Regions consisting essentially of silicon can be grown within the recesses to form embedded silicon regions. Source and drain regions then can be formed in the embedded silicon regions. The difference between the lattice constant of silicon and that of the underlying first and second regions results in tensile stressed silicon over the first semiconductor region and compressive stressed silicon over the second semiconductor region.
摘要翻译：提供了制造互补应力半导体器件的方法，例如具有拉伸应力通道的NFET和具有压应力通道的PFET。在这种方法中，可以在衬底的下面的半导体区域外延生长具有大于硅的晶格常数的第一半导体区域。第一半导体区域可以与具有比硅的晶格常数小的晶格常数的第二半导体区域横向生长。基本上由硅组成的层可以外延生长到第一和第二半导体区域的暴露的主表面上，之后可以形成覆盖外延生长的硅层的栅极。可以去除与栅极相邻的第一和第二半导体区域的部分以形成凹部。基本上由硅组成的区域可以在凹槽内生长以形成嵌入的硅区域。然后可以在嵌入的硅区域中形成源区和漏区。硅的晶格常数和下面的第一和第二区域的晶格常数之间的差异导致第一半导体区域上的拉伸应力硅和第二半导体区域上的压应力硅。

39. 发明授权

US07479689B2 Electronically programmable fuse having anode and link surrounded by low dielectric constant material 失效
标题翻译：具有由低介电常数材料包围的阳极和链节的电子可编程保险丝
公开(公告)号：US07479689B2
公开(公告)日：2009-01-20
申请号：US11627384
申请日：2007-01-26
申请人： Deok-Kee Kim , Xiangdong Chen , Haining Yang
发明人： Deok-Kee Kim , Xiangdong Chen , Haining Yang
IPC分类号： H01L23/58
CPC分类号： H01L23/5256 , H01L2924/0002 , H01L2924/00
摘要： An electronically programmable fuse (e-fuse) is disclosed. In one embodiment, the e-fuse includes a cathode surrounded only by silicon dioxide; an anode; and a polysilicon-silicide programmable link coupling the anode and the cathode, wherein the anode and the polysilicon-silicide programmable link are surrounded by a low dielectric constant (low-k) material on a top and a side thereof.
摘要翻译：公开了一种电子可编程保险丝（e-fuse）。在一个实施例中，电熔丝包括仅被二氧化硅包围的阴极; 阳极; 以及耦合所述阳极和所述阴极的多晶硅硅化物可编程链路，其中所述阳极和所述多晶硅硅化物可编程链路被其顶部和侧面上的低介电常数（低k）材料围绕。

40. 发明申请

US20080191284A1 METHOD FOR IMPROVED FABRICATION OF A SEMICONDUCTOR USING A STRESS PROXIMITY TECHNIQUE PROCESS 失效
标题翻译：使用应力近似技术方法改进制造半导体的方法
公开(公告)号：US20080191284A1
公开(公告)日：2008-08-14
申请号：US11672572
申请日：2007-02-08
申请人： Christopher Vincent Baiocco , Xiangdong Chen , Wenzhi Gao , Young Gun Ko , Young Way Teh
发明人： Christopher Vincent Baiocco , Xiangdong Chen , Wenzhi Gao , Young Gun Ko , Young Way Teh
IPC分类号： H01L27/092 , H01L21/8238
CPC分类号： H01L21/823807 , H01L21/31155 , H01L21/823864 , H01L29/7843 , Y10S438/938
摘要： An improved method for applying stress proximity technique process on a semiconductor device and the improved device is disclosed. In one embodiment, the method utilizes an additional set of sidewall spacers on one or more NFET devices during the fabrication process. This protects the one or more of the NFET devices during the activation of a compressive PFET stress liner, thereby reducing the compressive forces on the one or more NFET devices, and creating a semiconductor device with improved performance.
摘要翻译：公开了一种用于在半导体器件和改进的器件上应用应力接近技术工艺的改进方法。在一个实施例中，该方法在制造过程中在一个或多个NFET器件上利用附加的一组侧壁间隔物。这在保护压电PFET应力衬垫的激活期间保护一个或多个NFET器件，由此降低一个或多个NFET器件上的压缩力，并且产生具有改进性能的半导体器件。

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