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    • 31. 发明授权
    • Circuit for asynchronous communications, related system and method
    • 异步通信电路,相关系统及方法
    • US09191033B2
    • 2015-11-17
    • US13854419
    • 2013-04-01
    • STMicroelectronics S.r.l.
    • Daniele ManganoSalvatore PisasaleCarmelo Pistritto
    • H04L27/00H03M13/00H03M13/51G06F13/42
    • H03M13/6522G06F13/4286H03M13/51
    • A completion-detector circuit for detecting completion of the transfer of asynchronous data on a communication channel with signal lines organized according to a delay-insensitive encoding (e.g., dual-rail, m-of-n, Berger encoding) comprises: logic circuitry for detecting the data on the aforesaid signal lines configured for: i) producing a first signal indicating the fact that the asynchronous data on the signal lines are stable; ii) producing a second signal indicating the fact that the signal lines are de-asserted; and an asynchronous finite-state machine supplied with the first signal and the second signal for producing a signal of detection of completion of transfer of the asynchronous data, the detection signal having: a first value, when the first signal is asserted; and a second value, when the second signal is asserted; and being on hold when neither one nor the other of said first signal and said second signal is asserted.
    • 一种完成检测器电路,用于检测在根据延迟不敏感编码(例如,双轨,m-of-n,Berger编码)组织的信号线在通信信道上完成异步数据的传输,包括:用于 检测上述信号线上的数据,其配置用于:i)产生指示信号线上的异步数据是稳定的事实的第一信号; ii)产生指示信号线被断言的事实的第二信号; 以及提供有第一信号和第二信号的异步有限状态机,用于产生检测异步数据传输完成的信号,检测信号具有:第一值,当第一信号被断言时; 以及第二值,当所述第二信号被断言时; 并且当所述第一信号和所述第二信号的一个或另一个被断言时,它们处于保持状态。
    • 32. 发明授权
    • Method for handling access transactions and related system
    • 处理访问事务和相关系统的方法
    • US08990436B2
    • 2015-03-24
    • US13904379
    • 2013-05-29
    • STMicroelectronics S.r.l.
    • Daniele ManganoSalvatore PisasaleMirko Dondini
    • G06F3/00G06F9/46G06F13/16
    • G06F9/466G06F13/1626G06F2213/0038
    • In an embodiment, access transactions of at least one module of a system such as a System-on-Chip (SoC) to one of a plurality of target modules, such as memories, are managed by assigning transactions identifiers subjected to a consistency check. If an input identifier to the check has already been issued for the same given target module, to the related identifier/given target module pair the same input identifier is assigned as a consistent output identifier. If, on the contrary, said input identifier to the check has not been already issued or has already been issued for a target module different from the considered one, to the related identifier/given target module pair a new identifier, different from the input identifier, is assigned as a consistent output identifier.
    • 在一个实施例中,通过分配经过一致性检查的事务标识符来管理诸如片上系统(SoC)的系统的至少一个模块到诸如存储器的多个目标模块之一的访问事务。 如果已经为相同的给定目标模块发出了支票的输入标识符,则向相关标识符/给定目标模块对发送相同的输入标识符作为一致的输出标识符。 相反,如果相对于所述检查的所述输入标识符尚未被发布或者已经针对与所考虑的目标模块不同的目标模块已经被发布到相关标识符/给定目标模块对,则与输入标识符不同的新标识符 ,被分配为一致的输出标识符。
    • 33. 发明申请
    • METHOD AND SYSTEM FOR PERFORMING DIVISION/MULTIPLICATION OPERATIONS IN DIGITAL PROCESSORS, CORRESPONDING DEVICE AND COMPUTER PROGRAM PRODUCT
    • 在数字处理器,对应设备和计算机程序产品中执行部门/多媒体操作的方法和系统
    • US20140379769A1
    • 2014-12-25
    • US14313273
    • 2014-06-24
    • STMicroelectronics S.r.l.
    • Daniele Mangano
    • G06F5/01
    • G06F5/01G06F7/52G06F7/523G06F7/535
    • A digital processor, such as, e.g., a divider in a PID controller, performs a mathematical operation such as division (or multiplication) involving operands represented by strings of bit signals and an operator to produce an operation result. The processor is configured by identifying first and second power-of-two approximating values of the operator as the nearest lower and nearest higher power-of-two values to the operator. The operation is performed on the input operands by means of the first and second power-of-two approximating values of the operator by shifting the bit signals in the operands by using the first and second power-of-two approximating values in an alternated sequence to produce: first approximate results by using the first power-of-two approximating value, second approximate results by using the second power-of-two approximating value. The average of the first and second approximate results is representative of the accurate result of the operation.
    • 数字处理器,例如PID控制器中的分频器,执行数学运算,例如涉及由位信号串和运算符表示的操作数的除法(或乘法)以产生运算结果。 通过将操作者的第一和第二二次近似值识别为操作者的最接近的较低和最接近的较高功率值来配置处理器。 通过使用操作数中的位信号通过使用交替序列中的第一和第二二次近似值来通过操作者的第一和第二二次近似值对输入操作数执行操作 产生:通过使用第二二次近似值的第一近似结果,通过使用第二二次幂近似值的第二近似结果​​。 第一和第二近似结果​​的平均值代表操作的准确结果。