专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

31. 发明授权

US5001365A Logic circuit using bipolar and field effect transistor, including a delayed switching arrangement 失效
标题翻译：使用双极和场效应晶体管的逻辑电路，包括延迟的开关布置
公开(公告)号：US5001365A
公开(公告)日：1991-03-19
申请号：US325911
申请日：1989-03-20
申请人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
发明人： Fumio Murabayashi , Yoji Nishio , Shoichi Kotoku , Kozaburo Kurita , Kazuo Kato
IPC分类号： H01L29/73 , H01L21/331 , H01L21/82 , H01L27/06 , H01L27/118 , H01L29/732 , H03K17/04 , H03K17/16 , H03K17/567 , H03K19/00 , H03K19/003 , H03K19/08 , H03K19/0944
CPC分类号： H01L27/0623 , H03K19/001 , H03K19/00353 , H03K19/09448
摘要： A semiconductor integrated circuit device having a plurality of logic circuits integrated on a semiconductor substrate is provided which can operate with a power source potential difference substantially less than 5 V. The logic circuit includes a bipolar transistor having a base and its collector-emitter current path coupled between a first power source terminal and an output terminal, together with at least one field effect transistor having its gate responsive to an input signal applied to an input terminal and its source-drain current path coupled between the first power source terminal and the base of the bipolar transistor. A semiconductor switch means is also provided which is responsive to the input signal applied to the input terminal for performing ON/OFF operations complementary to the ON/OFF operations of the bipolar transistor and which has a current path between its paired main terminals coupled between the output terminal and the second power source terminal. In order to improve the operating speed, a potential difference reducing element is provided having a current path between its paired main terminals coupled between the first power source terminal and the output terminal for reducing the potential difference, which is present between the first power source terminal and the output terminal based on the base-emitter forward voltage of the bipolar transistor when the bipolar transistor is ON.
摘要翻译：提供了具有集成在半导体衬底上的多个逻辑电路的半导体集成电路器件，其可以以基本上小于5V的电源电位差工作。逻辑电路包括具有基极和其集电极 - 发射极电流路径的双极晶体管耦合在第一电源端子和输出端子之间，以及至少一个具有栅极的场效应晶体管，其响应于施加到输入端子的输入信号及其耦合在第一电源端子和基极之间的源极 - 漏极电流路径的双极晶体管。还提供半导体开关装置，其响应于施加到输入端子的输入信号，用于执行与双极晶体管的导通/截止操作互补的ON / OFF操作，并且在其双绞主端子之间具有电流通路输出端子和第二电源端子。为了提高工作速度，提供了一个电位差降低元件，其具有耦合在第一电源端子和输出端子之间的成对主端子之间的电流路径，用于减小电位差，该电位差存在于第一电源端子以及当双极晶体管导通时基于双极晶体管的基极 - 发射极正向电压的输出端子。

IPRDB

热门服务

关于我们

友情链接

联系方式