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31. 发明授权

US06518827B1 Sense amplifier threshold compensation 有权
标题翻译：感应放大器阈值补偿
公开(公告)号：US06518827B1
公开(公告)日：2003-02-11
申请号：US09917059
申请日：2001-07-27
申请人： John A. Fifield , Robert H. Dennard , Russell J. Houghton , Toshiaki Kirihara , Wing Luk
发明人： John A. Fifield , Robert H. Dennard , Russell J. Houghton , Toshiaki Kirihara , Wing Luk
IPC分类号： H03K301
CPC分类号： G11C7/04 , G11C7/06 , G11C11/4091 , G11C2207/2254
摘要： A method and system are disclosed for adjusting the threshold in MOS devices, in particular for devices used in DRAM sense amplifiers. The effects of process and temperature variations on the threshold are compensated by a back-bias voltage. A comparison of an indicating voltage and a reference voltage is used to generate the back-bias voltage. The direction of back-bias voltage may be either in the backward, or in the forward bias direction.
摘要翻译：公开了用于调整MOS器件中的阈值的方法和系统，特别是用于DRAM读出放大器中的器件。工艺和温度变化对阈值的影响由反向偏置电压补偿。使用指示电压和参考电压的比较来产生反偏压。背向偏置电压的方向可以是向后偏置方向或向前偏置方向。

32. 发明授权

US06243283B1 Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US06243283B1
公开(公告)日：2001-06-05
申请号：US09589922
申请日：2000-06-07
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： G11C506
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011 , H01L2924/00 , H01L2924/00012
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

33. 发明授权

US6141245A Impedance control using fuses 有权
标题翻译：使用熔断器进行阻抗控制
公开(公告)号：US6141245A
公开(公告)日：2000-10-31
申请号：US302902
申请日：1999-04-30
申请人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
发明人： Claude Louis Bertin , John A. Fifield , Erik Leigh Hedberg , Russell J. Houghton , Timothy Dooling Sullivan , Steven William Tomashot , William Robert Tonti
IPC分类号： H01L27/02 , G11C17/16 , H01L25/065 , G11C16/04
CPC分类号： H01L23/481 , G11C17/16 , H01L25/0657 , H01L2224/06181 , H01L2224/13025 , H01L2224/16 , H01L2224/16145 , H01L2224/16225 , H01L2224/17181 , H01L2224/48227 , H01L2224/4826 , H01L2225/06517 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06589 , H01L2225/06596 , H01L2924/01012 , H01L2924/01019 , H01L2924/01046 , H01L2924/10253 , H01L2924/13091 , H01L2924/15192 , H01L2924/181 , H01L2924/3011
摘要： A system and method for reducing impedance loading of semiconductor integrated circuit devices implementing protective device structures that contributes to impedance loading at an I/O pad connection. The method comprises providing a fuse device between the I/O pad connection and the protective device; connecting a current source device associated with each fuse device in the integrated circuit, the current source device connected to one end of the fuse device; providing fuse selection circuit for activating current flow through a selected fuse device between the current source and the I/O connection, the current flow being of an amount sufficient for blowing the fuse and disconnecting the protective device from the circuit structure, thereby reducing impedance loading at the I/O connection. Such a system and method is employed in a memory system comprising integrated circuit chips disposed in a stacked relation, with each chip including: a layer of active circuitry formed at a first layer of each chip; a plurality of through conducting structures disposed substantially vertically through each chip for enabling electronic connection with active circuitry at the first layer; second conducting device disposed at an end of the through conducting structure at an opposite side of a chip for connection with a corresponding through conductive structure of an adjacent stacked chip, the stacked chip structure formed by aligning one or more through conducting structures and second conducting devices of adjacent chips, whereby a chip of the stack is electronically connected to active circuitry formed on other chips of the stack. The stacked chip structure is ideal for reducing data access latency in memory systems employing memory chips such as DRAM.
摘要翻译：一种用于减少半导体集成电路器件的阻抗负载的系统和方法，其实现了有助于I / O焊盘连接处的阻抗加载的保护器件结构。该方法包括在I / O焊盘连接和保护装置之间设置熔丝装置; 连接与所述集成电路中的每个熔丝装置相关联的电流源装置，所述电流源装置连接到所述熔丝装置的一端; 提供保险丝选择电路，用于在电流源和I / O连接之间激活通过选定的保险丝装置的电流流动，电流量足以吹入保险丝并将保护装置与电路结构断开，从而减少阻抗负载在I / O连接。这种系统和方法被用在包括以堆叠关系布置的集成电路芯片的存储器系统中，每个芯片包括：形成在每个芯片的第一层的有源电路层; 多个通过导电结构，其基本垂直设置穿过每个芯片，以使得能够与第一层处的有源电路电连接; 第二导电装置，其设置在通孔导电结构的与芯片相对侧的端部处，与相邻的堆叠芯片的相应的贯穿导电结构相连接，所述堆叠的芯片结构通过将一个或多个穿过导电结构和第二导电装置的相邻芯片，由此堆叠的芯片电连接到形成在堆叠的其他芯片上的有源电路。堆叠式芯片结构非常适用于采用诸如DRAM之类的存储器芯片的存储器系统中的数据访问延迟。

34. 发明授权

US06347058B1 Sense amplifier with overdrive and regulated bitline voltage 有权
标题翻译：具有过驱动和稳压位线电压的感应放大器
公开(公告)号：US06347058B1
公开(公告)日：2002-02-12
申请号：US09574806
申请日：2000-05-19
申请人： Russell J. Houghton , Christopher P. Miller
发明人： Russell J. Houghton , Christopher P. Miller
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C7/06 , G11C11/4091 , G11C11/4094
摘要： In many DRAM (Dynamic Random Access Memory) architectures, a sense amplifier detects and amplifies a small voltage differential between complementary bitline pairs to read from/write to a DRAM memory cell. The access speed of the DRAM is dependent on the speed of the transition, due to this amplification, of the bitline pairs from an equalized, pre-charged voltage level to final (within a given sensing cycle) high and low levels. The transition speed of the bitline pairs can be increased by providing a higher overdrive voltage to the sense amplifier. As DRAM technologies are scaled successively smaller, the overdrive voltage must be controlled to avoid compromising the reliability of the DRAM. Accordingly, the present invention relates to a DRAM circuit which provides a transiently higher overdrive voltage only during sensing. The overdrive is provided by a pre-charged capacitive source utilizing the circuit's natural capacitance. The pre-charged capacitive source and the high-going bitline are coupled to a common node during sensing. The amount of capacitance and the level of pre-charge voltage are determined so as to arrive at a target voltage on the common node. The target voltage may be adjusted so as to achieve the correct write-back voltage for the high-going bitline.
摘要翻译：在许多DRAM（动态随机存取存储器）结构中，读出放大器检测并放大互补位线对之间的小的电压差，以从DRAM存储单元读/写。 DRAM的存取速度取决于由均衡的预充电电压电平到最终（在给定的感测周期内）高电平和低电平的位线对的转换速度。可以通过向感测放大器提供更高的过驱动电压来增加位线对的转换速度。随着DRAM技术的缩小，必须控制过驱动电压，以避免损害DRAM的可靠性。因此，本发明涉及仅在感测期间提供瞬时更高的过驱动电压的DRAM电路。利用电路的自然电容，预充电电容源提供过驱动。在感测期间，预充电电容源和高速位线耦合到公共节点。确定电容量和预充电电压的水平以便达到公共节点上的目标电压。可以调整目标电压以便为高速位线获得正确的回写电压。

35. 发明授权

US06204723B1 Bias circuit for series connected decoupling capacitors 失效
公开(公告)号：US06204723B1
公开(公告)日：2001-03-20
申请号：US09303359
申请日：1999-04-29
申请人： Russell J. Houghton , Christopher P. Miller
发明人： Russell J. Houghton , Christopher P. Miller
IPC分类号： G05F302
CPC分类号： G11C11/4074 , G05F3/242
摘要： A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.

36. 发明授权

US06429730B2 Bias circuit for series connected decoupling capacitors 有权
标题翻译：串联连接去耦电容的偏置电路
公开(公告)号：US06429730B2
公开(公告)日：2002-08-06
申请号：US09871265
申请日：2001-05-31
申请人： Russell J. Houghton , Christopher P. Miller
发明人： Russell J. Houghton , Christopher P. Miller
IPC分类号： G05F302
CPC分类号： G11C11/4074 , G05F3/242
摘要： A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.
摘要翻译：一种用于向集成电路电压源提供去耦电容的半导体电路，其包括由在节点处串联连接的存储器单元的阵列和连接到节点处的存储器单元阵列的偏置电压源组成的去耦电容，节点处的电压电平低于电压源的电压电平。

37. 发明授权

US06271717B1 Bias circuit for series connected decoupling capacitors 失效
标题翻译：串联连接去耦电容的偏置电路
公开(公告)号：US06271717B1
公开(公告)日：2001-08-07
申请号：US09694243
申请日：2000-10-23
申请人： Russell J. Houghton , Christopher P. Miller
发明人： Russell J. Houghton , Christopher P. Miller
IPC分类号： G05F110
CPC分类号： G11C11/4074 , G05F3/242
摘要： A semiconductor circuit for providing decoupling capacitance to an integrated circuit voltage supply that includes a decoupling capacitance comprised of an array of memory cells connected in series at a node and a source of biasing voltage connected to the array of memory cells at the node for maintaining the voltage level at the node lower than the voltage level of the voltage supply.
摘要翻译：一种用于向集成电路电压源提供去耦电容的半导体电路，其包括由在节点处串联连接的存储器单元的阵列和连接到节点处的存储器单元阵列的偏置电压源组成的去耦电容，节点处的电压电平低于电压源的电压电平。

38. 发明授权

US4413191A Array word line driver system 失效
标题翻译：阵列字线驱动系统
公开(公告)号：US4413191A
公开(公告)日：1983-11-01
申请号：US260576
申请日：1981-05-05
申请人： Russell J. Houghton
发明人： Russell J. Houghton
IPC分类号： G11C11/414 , G11C11/413 , G11C11/415 , H01L21/8229 , H01L27/102 , H03K17/04 , H03K17/16 , H03K17/62
CPC分类号： G11C11/415
摘要： This invention provides a system for selectively driving one word line of a plurality of word lines in a memory array which includes a first highly capacitive common line connected to a plurality of driver circuits, each of which has connected to its output a respective word line and each of which includes a transistor having a capacitive junction connected to the common line. Means are provided for charging the common line and for rapidly discharging the common line through a selected driver circuit to its associated word line. Additionally, a second highly capacitive common line is connected to a point of reference potential through a resistor, with each of the driver circuits being connected between said first and second common lines.
摘要翻译：本发明提供了一种用于选择性地驱动存储器阵列中的多个字线的一条字线的系统，该系列包括连接到多个驱动器电路的第一高容性公共线，每个驱动电路已连接到其输出相应的字线，每个都包括具有连接到公共线的电容结的晶体管。提供了用于对公共线充电并且用于通过所选择的驱动器电路将公共线快速放电到其相关联的字线的装置。此外，第二高电容公共线通过电阻器连接到参考电位点，其中每个驱动电路连接在所述第一和第二公共线之间。

39. 发明授权

US06876250B2 Low-power band-gap reference and temperature sensor circuit 有权
标题翻译：低功率带隙参考和温度传感器电路
公开(公告)号：US06876250B2
公开(公告)日：2005-04-05
申请号：US10345039
申请日：2003-01-15
申请人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton
发明人： Louis L. Hsu , Rajiv V. Joshi , Russell J. Houghton
IPC分类号： G01K7/01 , G05F3/30 , H01L23/34 , G05F1/10
CPC分类号： G05F3/30 , G01K7/015 , H01L23/34 , H01L2924/0002 , H01L2924/00
摘要： A combined low-voltage, low-power band-gap reference and temperature sensor circuit is provided for providing a band-gap reference parameter and for sensing the temperature of a chip, such as an eDRAM memory unit or CPU chip, using the band-gap reference parameter. The combined sensor circuit is insensitive to supply voltage and a variation in the chip temperature. The power consumption of both circuits, i.e., the band-gap reference and the temperature sensor circuits, encompassing the combined sensor circuit is less than one μW. The combined sensor circuit can be used to monitor local or global chip temperature. The result can be used to (1) regulate DRAM array refresh cycle time, e.g., the higher the temperature, the shorter the refresh cycle time, (2) to activate an on-chip or off-chip cooling or heating device to regulate the chip temperature, (3) to adjust internally generated voltage level, and (4) to adjust the CPU (or microprocessor) clock rate, i.e., frequency, so that the chip will not overheat. The combined band-gap reference and temperature sensor circuit of the present invention can be implemented within battery-operated devices having at least one memory unit. The low-power circuits of the sensor circuit extend battery lifetime and data retention time of the cells of the at least one memory unit.
摘要翻译：提供了组合的低压，低功率带隙参考和温度传感器电路，用于提供带隙参考参数，并且用于使用频带参考参数来感测诸如eDRAM存储器单元或CPU芯片的芯片的温度，间隙参考参数。组合的传感器电路对电源电压和芯片温度的变化不敏感。包含组合传感器电路的两个电路（即带隙基准和温度传感器电路）的功耗小于1μW。组合传感器电路可用于监测局部或全局芯片温度。结果可用于（1）调节DRAM阵列刷新周期时间，例如温度越高，刷新周期时间越短，（2）启动片上或片外冷却或加热装置来调节芯片温度，（3）调节内部产生的电压电平，（4）调整CPU（或微处理器）的时钟频率，即频率，使芯片不会过热。本发明的组合带隙参考和温度传感器电路可以在具有至少一个存储器单元的电池供电的装置内实现。传感器电路的低功率电路延长了至少一个存储器单元的单元的电池寿命和数据保持时间。

40. 发明授权

US06570434B1 Method to improve charge pump reliability, efficiency and size 失效
公开(公告)号：US06570434B1
公开(公告)日：2003-05-27
申请号：US09662685
申请日：2000-09-15
申请人： Louis Hsu , Russell J. Houghton , Oliver Weinfurtner
发明人： Louis Hsu , Russell J. Houghton , Oliver Weinfurtner
IPC分类号： G05F302
CPC分类号： G11C5/145
摘要： A dynamic clamp is used in conjunction with capacitors with thinner dielectric or with deep trench capacitors to solve the problem of dielectric breakdown in high stress capacitors. The dynamic clamp is realized using a two stage pump operation cycle such that, during a first stage pump cycle, a middle node of a pair of series connected capacitors is pre-charged to a supply voltage and, during a second stage pump cycle, the middle node is coupled by a boost clock. Thus, at any moment in the pump operation cycle, the voltage across the capacitors is held within a safety range.

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