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31. 发明申请

US20080106552A1 DEFERRED PAGE FAULTING IN VIRTUAL MEMORY BASED SPARSE TEXTURE REPRESENTATIONS 有权
标题翻译：基于虚拟内存的虚拟纹理表示中的延迟页面分析
公开(公告)号：US20080106552A1
公开(公告)日：2008-05-08
申请号：US11611081
申请日：2006-12-14
申请人： Cass W. Everitt
发明人： Cass W. Everitt
IPC分类号： G06T11/40
CPC分类号： G06T11/001
摘要： A virtually-addressed local texture memory stores selected regions (a sparse representation) of a texture for use by a graphics processor. The graphics processor requests a texel of the texture by referencing a virtual address of the texel. A memory interface references an address map to determine whether the requested texel is in one of the regions of the texture that is resident in the local texture memory. If so, the texel is retrieved from the local memory and used in the rendering operation; if not, an alternative texel that is resident in the local memory is retrieved and used in the rendering operation. Non-resident regions that include requested texels are retrieved from a primary texture data store at regular intervals (e.g., once per frame) and stored in local texture memory for use in a subsequent rendering operation.
摘要翻译：虚拟寻址的本地纹理存储器存储由图形处理器使用的纹理的选定区域（稀疏表示）。图形处理器通过引用纹素的虚拟地址来请求纹理的纹理。存储器接口引用地址映射以确定所请求的纹素是否在驻留在本地纹理存储器中的纹理的区域之一中。如果是，则从本地存储器检索纹素，并在渲染操作中使用; 如果没有，则在渲染操作中检索并使用驻留在本地存储器中的替代纹理元素。包括所请求的纹素的非驻留区域以规则的间隔（例如，每帧一次）从主纹理数据存储器检索并存储在本地纹理存储器中，以用于随后的渲染操作。

32. 发明授权

US08862823B1 Compression status caching 有权
标题翻译：压缩状态缓存
公开(公告)号：US08862823B1
公开(公告)日：2014-10-14
申请号：US12340503
申请日：2008-12-19
申请人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
发明人： David B. Glasco , Cass W. Everitt , David Kirk Mcallister , Emmett M. Kilgariff , George R. Lynch , James Roberts , Karan Mehra , Patrick R. Marchand , Peter B. Holmqvist , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00 , G06F13/28
CPC分类号： G06F12/0897 , G06F12/0848 , G06F12/1009 , G06F12/123 , G06F2212/1041 , G06F2212/401 , G06F2212/455 , G06F2212/466 , G06T1/60
摘要： One embodiment of the present invention sets forth a compression status cache configured to store compression information for blocks of memory stored within an external memory. A data cache unit is configured to request, in response to a cache miss, compressed data from the external memory based on compression information stored in the compression status bit cache. The compression status for active buffers is dynamically swapped into the compression status cache as needed. Different compression formats may be specified for one or more tiles within an active buffer. One advantage of the disclosed compression status cache is that a lame amount of attached memory may be allocated as compressible memory blocks, without incurring a corresponding die area cost because a portion of the compression status stored off chip in attached memory is cached in the compression status cache.
摘要翻译：本发明的一个实施例提出了一种被配置为存储存储在外部存储器中的存储器块的压缩信息的压缩状态缓存。数据高速缓存单元被配置为基于存储在压缩状态位高速缓存中的压缩信息，响应于高速缓存未命中来请求来自外部存储器的压缩数据。活动缓冲区的压缩状态根据需要动态交换到压缩状态缓存。可以为活动缓冲区内的一个或多个瓦片指定不同的压缩格式。所公开的压缩状态高速缓存的一个优点是可以将大量附加存储器分配为可压缩存储器块，而不会引起相应的管芯区域成本，因为存储在附加存储器中的芯片外的存储器的一部分被缓存在压缩状态缓存。

33. 发明授权

US08441487B1 Bandwidth compression for shader engine store operations 有权
标题翻译：着色引擎存储操作的带宽压缩
公开(公告)号：US08441487B1
公开(公告)日：2013-05-14
申请号：US11830776
申请日：2007-07-30
申请人： Cass W. Everitt
发明人： Cass W. Everitt
IPC分类号： G06T1/00
CPC分类号： G06T9/00
摘要： Embodiments of the present invention set forth systems and methods for compressing thread group data written to frame buffer memory to increase overall memory performance. A compression/decompression engine within the frame buffer memory interface includes logic configured to identify situations where the threads of a thread group are writing similar scalar values to memory. Upon recognizing such a situation, the engine is configured to compress the scalar data into a form that allows all of the scalar data to be written to or read from the frame buffer memory in fewer clock cycles than would be required to transmit the data in uncompressed form to or from memory. Consequently, the disclosed systems and methods are able to effectively increase memory performance when executing thread group STORE and LOAD operations.
摘要翻译：本发明的实施例提出了将写入帧缓冲存储器的线程组数据压缩以增加总体存储器性能的系统和方法。帧缓冲存储器接口内的压缩/解压缩引擎包括被配置为识别线程组的线程将相似标量值写入存储器的情况的逻辑。在识别到这种情况之后，引擎被配置为将标量数据压缩成允许所有标量数据以比未压缩的数据传输所需的更少的时钟周期写入或从帧缓冲存储器读取的形式形式到或来自记忆。因此，所公开的系统和方法能够在执行线程组存储和加载操作时有效地增加存储器性能。

34. 发明授权

US08212825B1 System and method for geometry shading 有权
标题翻译：几何阴影的系统和方法
公开(公告)号：US08212825B1
公开(公告)日：2012-07-03
申请号：US11945995
申请日：2007-11-27
申请人： Cass W. Everitt , Henry Packard Moreton
发明人： Cass W. Everitt , Henry Packard Moreton
IPC分类号： G06F15/80
CPC分类号： G06T15/005 , G06T2210/52
摘要： One embodiment of the present invention sets forth a technique for more effectively utilizing graphics hardware by allowing the developer to exploit parallelism at the primitive-level. In this technique, an algorithm is analyzed to break the total work associated with processing one primitive into discrete portions of work. The results of this analysis are used to program a geometry shader group that includes multiple geometry shaders. Upon receiving a single input primitive, the geometry shader group launches multiple parallel threads, one thread in each geometry shader in the group corresponding to each discrete portion of work. As each thread completes, the output of the thread is stored in on-chip GPU memory for processing by the next stage in the graphics pipeline. Since the overall work associated with a given input primitive is distributed across multiple threads, the output of each thread is smaller and, thus, the total memory required to implement the algorithm is reduced.
摘要翻译：本发明的一个实施例提出了一种通过允许开发人员在原始级别利用并行性来更有效地利用图形硬件的技术。在这种技术中，分析了一种算法，以将与处理一个原语相关的总工作分解成离散的工作部分。该分析的结果用于对包含多个几何着色器的几何着色器组进行编程。在接收到单个输入基元时，几何着色器组将启动多个并行线程，该组中每个几何着色器中的一个线程对应于每个离散的工作部分。当每个线程完成时，线程的输出被存储在片上GPU存储器中，以在图形流水线中的下一阶段进行处理。由于与给定输入原语相关联的整体工作分布在多个线程上，所以每个线程的输出较小，从而减少了实现算法所需的总内存。

35. 发明授权

US08102393B1 Cull streams for fine-grained rendering predication 有权
标题翻译：用于细粒度渲染预测的Cull流
公开(公告)号：US08102393B1
公开(公告)日：2012-01-24
申请号：US11956308
申请日：2007-12-13
申请人： Cass W. Everitt , Franck R. Diard
发明人： Cass W. Everitt , Franck R. Diard
IPC分类号： G06T15/40 , G06T15/50 , G06T15/10 , G06F15/80 , G06F13/14
CPC分类号： G06T15/005 , G06T15/40
摘要： One embodiment of the present invention sets forth a technique to perform fine-grained rendering predication using an IGPU and a DGPU. A graphics driver divides a 3D object into batches of triangles. The IGPU processes each batch of triangles through a modified rendering pipeline to determine if the batch is culled. The IGPU writes bits into a bitstream corresponding to the visibility of the batches. The DGPU reads bits from the bitstream and performs full-blown rendering, including shading, but only on the batches of triangles whose bit indicates that the batch is visible. Advantageously, this approach to rendering predication provides fine-grained culling without adding unnecessary overhead, thereby optimizing both hardware resources and performance.
摘要翻译：本发明的一个实施例提出了使用IGPU和DGPU执行细粒度渲染预测的技术。图形驱动程序将3D对象分成三个三角形。 IGPU通过修改的渲染管线处理每批三角形，以确定批次是否被剔除。 IGPU将比特写入与批次的可见性相对应的比特流中。 DGPU从比特流中读取比特流，并执行完整的渲染，包括着色，但仅在批次可以看到的批次的三角形中。有利地，这种渲染预测的方法提供了细粒度的淘汰，而不会增加不必要的开销，从而优化硬件资源和性能。

36. 发明授权

US09652815B2 Texel data structure for graphics processing unit programmable shader and method of operation thereof 有权
公开(公告)号：US09652815B2
公开(公告)日：2017-05-16
申请号：US13609698
申请日：2012-09-11
申请人： Cass W. Everitt , Henry P. Moreton
发明人： Cass W. Everitt , Henry P. Moreton
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00 , G06T15/04 , G06F12/1027
CPC分类号： G06T1/20 , G06F12/1027 , G06T1/60 , G06T15/005 , G06T15/04
摘要： A graphics processing subsystem and a method of shading are provided. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to create the particular composite texel.

37. 发明申请

US20140071128A1 TEXEL DATA STRUCTURE FOR GRAPHICS PROCESSING UNIT PROGRAMMABLE SHADER AND METHOD OF OPERATION THEREOF 有权
标题翻译：图形处理单元的TEXEL数据结构可编程阴影及其操作方法
公开(公告)号：US20140071128A1
公开(公告)日：2014-03-13
申请号：US13609698
申请日：2012-09-11
申请人： Cass W. Everitt , Henry P. Moreton
发明人： Cass W. Everitt , Henry P. Moreton
IPC分类号： G06T15/60
CPC分类号： G06T1/20 , G06F12/1027 , G06T1/60 , G06T15/005 , G06T15/04
摘要： A graphics processing subsystem and a method of shading. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to create the particular composite texel.
摘要翻译：图形处理子系统和阴影方法。在一个实施例中，子系统包括：（1）被配置为包含纹素数据结构的存储器，根据该纹理数据结构，存储器的单个页面中包含与特定复合纹素相对应的多个基本纹理元素，以及（2）配置的图形处理单元通过数据总线与存储器进行通信，并执行着色器以获取单页中包含的多个原始纹素，以创建特定的复合纹理。

38. 发明授权

US08627041B2 Efficient line and page organization for compression status bit caching 有权
标题翻译：用于压缩状态位缓存的高效线和页组织
公开(公告)号：US08627041B2
公开(公告)日：2014-01-07
申请号：US12901452
申请日：2010-10-08
申请人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
发明人： David B. Glasco , Peter B. Holmqvist , George R. Lynch , Patrick R. Marchand , Karan Mehra , James Roberts , Cass W. Everitt , Steven E. Molnar
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/08 , G06F12/0875 , G06F12/1009 , G06F2212/401
摘要： One embodiment of the present invention sets forth a technique for performing a memory access request to compressed data within a virtually mapped memory system comprising an arbitrary number of partitions. A virtual address is mapped to a linear physical address, specified by a page table entry (PTE). The PTE is configured to store compression attributes, which are used to locate compression status for a corresponding physical memory page within a compression status bit cache. The compression status bit cache operates in conjunction with a compression status bit backing store. If compression status is available from the compression status bit cache, then the memory access request proceeds using the compression status. If the compression status bit cache misses, then the miss triggers a fill operation from the backing store. After the fill completes, memory access proceeds using the newly filled compression status information.
摘要翻译：本发明的一个实施例提出了一种对包括任意数量的分区的虚拟映射的存储器系统中的压缩数据执行存储器访问请求的技术。虚拟地址被映射到由页表项（PTE）指定的线性物理地址。 PTE被配置为存储压缩属性，其用于定位压缩状态位缓存内的对应物理存储器页的压缩状态。压缩状态位缓存与压缩状态位后备存储一起操作。如果从压缩状态位缓存获得压缩状态，则存储器访问请求使用压缩状态进行。如果压缩状态位缓存未命中，则错误触发后备存储器的填充操作。填充完成后，使用新填充的压缩状态信息进行内存访问。

39. 发明授权

US08605087B2 Hybrid multisample/supersample antialiasing 有权
公开(公告)号：US08605087B2
公开(公告)日：2013-12-10
申请号：US12167998
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50
CPC分类号： G06T15/503 , G06T11/40 , G06T2200/28 , G06T2210/52
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.

40. 发明授权

US08605086B2 Hybrid multisample/supersample antialiasing 有权
标题翻译：混合多采样/超采样抗锯齿
公开(公告)号：US08605086B2
公开(公告)日：2013-12-10
申请号：US12167997
申请日：2008-07-03
申请人： Cass W. Everitt , Steven E. Molnar
发明人： Cass W. Everitt , Steven E. Molnar
IPC分类号： G06T15/50
CPC分类号： G06T11/40
摘要： A system and method for dynamically adjusting the pixel sampling rate during primitive shading can improve image quality or increase shading performance. Hybrid antialiasing is performed by selecting a number of shaded samples per pixel fragment. A combination of supersample and multisample antialiasing is used where a cluster of sub-pixel samples (multisamples) is processed for each pass through a fragment shader pipeline. The number of shader passes and multisamples in each cluster can be determined dynamically for each primitive based on rendering state.
摘要翻译：在原始着色中动态调整像素采样率的系统和方法可以提高图像质量或增加遮蔽性能。通过选择每个像素片段的阴影样本数来执行混合抗混叠。使用超采样和多采样抗锯齿的组合，其中对于通过片段着色器管线的每次通过处理子像素采样（多采样）的簇。可以基于呈现状态为每个基元动态地确定每个集群中的着色器遍数和多个样本的数量。

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