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31. 发明授权

US07694203B2 On-chip samplers for asynchronously triggered events 有权
标题翻译：用于异步触发事件的片上采样器
公开(公告)号：US07694203B2
公开(公告)日：2010-04-06
申请号：US11773020
申请日：2007-07-03
申请人： Frankie Y. Liu , Ronald Ho , Robert J. Drost
发明人： Frankie Y. Liu , Ronald Ho , Robert J. Drost
IPC分类号： G01R31/28
CPC分类号： G01R31/31705 , G01R19/0053 , G01R31/2884
摘要： Embodiments of an integrated circuit that includes a debug circuit are described. This debug circuit is configured to test an asynchronous circuit by performing analog measurements on asynchronous signals associated with the asynchronous circuit, and includes a triggering module configured to gate the debug circuit based on one or more of the asynchronous signals. This triggering module has a continuous mode of operation and a single-shot mode of operation. A timing module within the debug circuit has a timing range exceeding a pre-determined value, and is configured to provide signals corresponding to a first time base or signals corresponding to a second time base. Furthermore, control logic within the debug circuit is configured to select a mode of operation and a given time base for the debug circuit, which is either the first time base or the second time base.
摘要翻译：描述包括调试电路的集成电路的实施例。该调试电路被配置为通过对与异步电路相关联的异步信号执行模拟测量来测试异步电路，并且包括被配置为基于一个或多个异步信号门控调试电路的触发模块。该触发模块具有连续的操作模式和单次操作模式。调试电路内的定时模块具有超过预定值的定时范围，并且被配置为提供对应于第一时基的信号或对应于第二时基的信号。此外，调试电路内的控制逻辑被配置为选择作为第一时基或第二时基的调试电路的操作模式和给定时基。

32. 发明授权

US07646984B1 Clocking of integrated circuits using photonics 有权
标题翻译：使用光子学的集成电路的时钟
公开(公告)号：US07646984B1
公开(公告)日：2010-01-12
申请号：US11728915
申请日：2007-03-26
申请人： Ronald Ho , John E. Cunningham , Ashok V. Krishnamoorthy , Robert J. Drost
发明人： Ronald Ho , John E. Cunningham , Ashok V. Krishnamoorthy , Robert J. Drost
IPC分类号： H04B10/12
CPC分类号： G06F1/105
摘要： Embodiments of an integrated circuit are described. This integrated circuit includes: a clock-generator circuit configured to provide a clock signal; an optical clock path coupled to the clock-generator circuit; and a latch coupled to the optical clock path. This optical clock path is configured to distribute an optical signal corresponding to the clock signal. Furthermore, the optical clock path is configured to optically set a skew value for the optical signal, and is configured to selectively gate distribution of the optical signal to the latch based on activity of the latch. Note that the selective gating is performed optically.
摘要翻译：描述集成电路的实施例。该集成电路包括：时钟发生器电路，被配置为提供时钟信号; 耦合到时钟发生器电路的光时钟通路; 以及耦合到光时钟路径的锁存器。该光时钟路径被配置为分配对应于时钟信号的光信号。此外，光时钟路径被配置为光学地设置光信号的偏斜值，并且被配置为基于锁存器的活动来选择性地将光信号分配到锁存器。注意，选择性门控是光学执行的。

33. 发明申请

US20090189674A1 Circuit that facilitates proximity communication 有权
标题翻译：促进接近通信的电路
公开(公告)号：US20090189674A1
公开(公告)日：2009-07-30
申请号：US12215943
申请日：2008-06-30
申请人： Alex Chow , Robert J. Drost , Ronald Ho , Robert Proebsting , Arlene Proebsting
发明人： Alex Chow , Robert J. Drost , Ronald Ho , Robert Proebsting , Arlene Proebsting
IPC分类号： H03K17/16
CPC分类号： H01L23/48 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates proximity communication. This system includes a circuit containing a bootstrap transistor and a pass-gate transistor, where the drain of the bootstrap transistor is coupled to the gate of the pass-gate transistor. Note that a first coupling capacitance exists between the source of the pass-gate transistor and the drain of the bootstrap transistor and a second coupling capacitance exists between the drain of the pass-gate transistor and the drain of the bootstrap transistor. During operation, the gate and the source of the bootstrap transistor are coupled to a high voltage, thereby causing an intermediate voltage at the drain of the bootstrap transistor. When the source of the pass-gate transistor transitions to a high voltage, the first coupling capacitance and the second coupling capacitance boost the voltage at the gate of the pass-gate transistor higher than the high voltage, thereby enabling the high voltage at the source of the pass-gate transistor to pass to the drain of the pass-gate transistor.
摘要翻译：本发明的一个实施例提供一种便于邻近通信的系统。该系统包括包含自举晶体管和通过栅极晶体管的电路，其中自举晶体管的漏极耦合到栅极 - 栅极晶体管的栅极。注意，在栅极晶体管的源极和自举晶体管的漏极之间存在第一耦合电容，并且在通过栅极晶体管的漏极和自举晶体管的漏极之间存在第二耦合电容。在操作期间，自举晶体管的栅极和源极耦合到高电压，从而在自举晶体管的漏极处产生中间电压。当栅极晶体管的源极转换到高电压时，第一耦合电容和第二耦合电容使得栅极晶体管的栅极处的电压升高到高于高电压，从而使源极处的高电压的栅极晶体管传递到栅极晶体管的漏极。

34. 发明授权

US07356213B1 Transparent switch using optical and electrical proximity communication 有权
标题翻译：透明开关采用光电接近通讯
公开(公告)号：US07356213B1
公开(公告)日：2008-04-08
申请号：US11728843
申请日：2007-03-26
申请人： John E. Cunningham , Ashok V. Krishnamoorthy , Ronald Ho , Robert J. Drost
发明人： John E. Cunningham , Ashok V. Krishnamoorthy , Ronald Ho , Robert J. Drost
IPC分类号： G02B6/12
CPC分类号： H01L23/48 , H01L25/0652 , H01L25/0657 , H01L2225/06513 , H01L2225/06527 , H01L2924/0002 , H01L2924/00
摘要： Embodiments of a switch are described. This switch includes input ports configured to receive signals (which include data) and output ports configured to output the signals. In addition, the switch includes switching elements and a flow-control mechanism, which is configured to provide flow-control information associated with the data to the switching elements via an optical control path. These switching elements are configured to selectively couple the input ports to the output ports based on the flow-control information. Furthermore, a given switching element in the switching elements is coupled to a given input port and a given output port via electrical signal paths that are configured to use proximity communication to communicate the data.
摘要翻译：描述开关的实施例。该开关包括被配置为接收被配置为输出信号的信号（其包括数据）和输出端口的输入端口。此外，开关包括开关元件和流量控制机构，其被配置为经由光学控制路径向开关元件提供与数据相关联的流量控制信息。这些开关元件被配置为基于流量控制信息选择性地将输入端口耦合到输出端口。此外，开关元件中的给定开关元件通过经配置以使用接近通信来传送数据的电信号路径耦合到给定输入端口和给定输出端口。

35. 发明授权

US07332919B1 Method and apparatus for distributing signals over jig-plates 有权
标题翻译：用于在夹具板上分配信号的方法和装置
公开(公告)号：US07332919B1
公开(公告)日：2008-02-19
申请号：US11232843
申请日：2005-09-21
申请人： Ronald Ho , Robert J. Drost , Arthur R. Zingher
发明人： Ronald Ho , Robert J. Drost , Arthur R. Zingher
IPC分类号： G01R31/02
CPC分类号： H01L23/538 , H01L25/0655 , H01L2924/0002 , H01L2924/14 , H01L2924/30105 , H01L2924/30107 , H05K1/0287 , H05K1/0289 , H05K1/183 , H05K2201/09254 , H05K2201/10674 , H01L2924/00
摘要： One embodiment of the present invention provides a system for distributing signals through a jig-plate in a computer system. The jig-plate contains alignment features that assist in positioning semiconductor chips in relation to the jig-plate. In addition, the jig-plate contains one or more embedded signal routing layers. These metal routing layers provide one or more signal routes for the distribution of signals through the jig-plate to semiconductor chips which have been aligned with the jig-plate. Note that routing the signals through the jig-plate facilitates the distribution of the signals without requiring that the signals be routed through the semiconductor chips in the jig-plate.
摘要翻译：本发明的一个实施例提供一种用于通过计算机系统中的夹具板来分配信号的系统。夹具板包含有助于相对于夹具板定位半导体芯片的对准特征。另外，夹具板包含一个或多个嵌入式信号路由层。这些金属布线层提供了一个或多个用于将通过夹具板的信号分配到已经与夹具板对准的半导体芯片的信号路线。注意，通过夹具板布置信号有助于信号的分配，而不需要信号通过夹具板中的半导体芯片布线。

36. 发明授权

US07200830B2 Enhanced electrically-aligned proximity communication 有权
标题翻译：增强的电对齐邻近通信
公开(公告)号：US07200830B2
公开(公告)日：2007-04-03
申请号：US10879607
申请日：2004-06-28
申请人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
发明人： Robert J. Drost , Ivan E. Sutherland , Ronald Ho
IPC分类号： G06F17/50
CPC分类号： H01L23/48 , H01L25/0657 , H01L2225/06531 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that facilitates capacitive inter-chip communication. During operation, the system first determines an alignment between a first semiconductor die and a second semiconductor die. Next, electrical signals are selectively routed to at least one interconnect pad in a plurality of interconnect pads based on the alignment thereby facilitating communication between the first semiconductor die and the second semiconductor die. The plurality of interconnect pads can include transmitting pads, receiving pads, and transmitting and receiving pads. The alignment may be determined continuously or at times separated by an interval, where the interval is fixed or variable. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种便于电容芯片间通信的系统。在操作期间，系统首先确定第一半导体管芯和第二半导体管芯之间的对准。接下来，基于对准，电信号被选择性地路由到多个互连焊盘中的至少一个互连焊盘，从而便于第一半导体管芯和第二半导体管芯之间的连通。多个互连焊盘可以包括传输焊盘，接收焊盘以及发射和接收焊盘。可以连续地或有时间隔地间隔地确定对准，其中间隔是固定的或可变的。提供了该实施例的几个变型。

37. 发明授权

US07148074B1 Method and apparatus for using a capacitor array to measure alignment between system components 有权
标题翻译：使用电容器阵列来测量系统部件之间的对准的方法和装置
公开(公告)号：US07148074B1
公开(公告)日：2006-12-12
申请号：US10820662
申请日：2004-04-07
申请人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
发明人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
IPC分类号： G01R31/26 , H01L21/66
CPC分类号： H01L25/50 , H01L25/0657 , H01L2225/06513 , H01L2225/06531 , H01L2225/06534 , H01L2225/06593 , H01L2924/0002 , H01L2924/00
摘要： One embodiment of the present invention provides a system that measures alignment between a first semiconductor die and a second semiconductor die. The system operates by applying a pattern of voltage signals to a two-dimensional array of conductive transmitter elements that form a transmitter array on the first semiconductor die. This transmitter array is positioned over a corresponding two-dimensional array of conductive receiver elements that form a receiver array on the second semiconductor die, whereby a voltage signal applied to a transmitter element induces a voltage signal in one or more receiver elements. The system amplifies voltage signals induced in receiver elements in the receiver array, and subsequently analyzes the amplified signals to determine an alignment between the first semiconductor die and the second semiconductor die.
摘要翻译：本发明的一个实施例提供一种测量第一半导体管芯和第二半导体管芯之间的对准的系统。该系统通过将电压信号的图案应用于在第一半导体管芯上形成发射器阵列的导电发射器元件的二维阵列来进行操作。该发射器阵列位于形成第二半导体管芯上的接收器阵列的导电接收器元件的对应的二维阵列上，由此施加到发射器元件的电压信号在一个或多个接收器元件中感应电压信号。该系统放大在接收器阵列中的接收器元件中感应的电压信号，随后分析放大的信号以确定第一半导体管芯和第二半导体管芯之间的对准。

38. 发明授权

US07106079B2 Using an interposer to facilate capacitive communication between face-to-face chips 有权
标题翻译：使用插入器来提升面对面芯片之间的电容性通信
公开(公告)号：US07106079B2
公开(公告)日：2006-09-12
申请号：US10973114
申请日：2004-10-22
申请人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
发明人： Robert J. Drost , Ronald Ho , Robert J. Proebsting
IPC分类号： G01R31/00
CPC分类号： H01L23/48 , H01L23/49827 , H01L23/49833 , H01L23/552 , H01L24/72 , H01L24/73 , H01L25/0652 , H01L25/0657 , H01L25/50 , H01L2225/06527 , H01L2225/06541 , H01L2225/06555 , H01L2225/06562 , H01L2225/06572 , H01L2924/01005 , H01L2924/01006 , H01L2924/01027 , H01L2924/01033 , H01L2924/01082 , H01L2924/14 , H01L2924/15153 , H01L2924/15165 , H01L2924/19041 , H01L2924/30105
摘要： A system that improves communications between capacitively coupled integrated circuit chips. The system operates by situating an interposer over capacitive communication pads on a first integrated circuit chip, wherein the interposer is made up of material that is anisotropic with respect to transmitting capacitive signals. A second integrated circuit chip is situated so that communication pads on the second integrated circuit chip are aligned to capacitively couple signals between the integrated circuit chips through the interposer. The increased dielectric permittivity caused by the interposer can improve capacitive coupling between opposing communication pads on the integrated circuit chips. The interposer can also reduce cross talk between communication pads on the first integrated circuit chip and pads adjacent to the opposing communication pads on the second integrated circuit chip.
摘要翻译：一种改善电容耦合集成电路芯片之间通信的系统。该系统通过在第一集成电路芯片上的电容性通信焊盘上设置插入器来工作，其中插入器由相对于传输电容性信号是各向异性的材料构成。第二集成电路芯片被定位成使得第二集成电路芯片上的通信焊盘对齐以通过插入器电容耦合在集成电路芯片之间的信号。由插入器引起的增加的介电常数可以改善集成电路芯片上相对的通信焊盘之间的电容耦合。插入器还可以减少第一集成电路芯片上的通信焊盘与第二集成电路芯片上相对的通信焊盘相邻的焊盘之间的串扰。

39. 发明授权

US07085178B1 Low-power memory write circuits 有权
标题翻译：低功耗存储器写入电路
公开(公告)号：US07085178B1
公开(公告)日：2006-08-01
申请号：US11045940
申请日：2005-01-27
申请人： Robert J. Proebsting , Ronald Ho , Robert J. Drost
发明人： Robert J. Proebsting , Ronald Ho , Robert J. Drost
IPC分类号： G11C7/00
CPC分类号： G11C7/1078 , G11C7/1048 , G11C7/1096 , G11C2207/2227
摘要： One embodiment of the present invention provides a system that writes to a cell in a memory using a low-voltage-swing signal across a pair of global bit-lines. During operation, the system receives a low-voltage-swing signal across a pair of global bit-lines, which is too low to reliably write the memory cell. Next, the system converts the low-voltage-swing signal to a high-voltage-swing signal, which is adequate to reliably write the memory cell. The system then writes to the memory cell by applying the high-voltage-swing signal across a pair of local bit-lines that are coupled to the memory cell. The use of low-voltage-swing signals on the global bit-lines reduces overall power consumption. Furthermore, in one embodiment of the present invention, the voltage conversion is achieved using a pair of cross-coupled NMOS transistors whose sources are directly or indirectly coupled with the global bit-lines, and whose drains are directly or indirectly coupled with the local bit-lines.
摘要翻译：本发明的一个实施例提供一种使用跨越一对全局位线的低电压摆幅信号向存储器中的单元写入的系统。在运行期间，系统通过一对全局位线接收低电压摆幅信号，该位线太低而无法可靠地写存储单元。接下来，系统将低电压摆幅信号转换成高电压摆幅信号，这足以可靠地写入存储单元。然后，系统通过将耦合到存储器单元的一对本地位线施加高电压摆幅信号来写入存储器单元。在全局位线上使用低电压摆幅信号可以降低总体功耗。此外，在本发明的一个实施例中，使用一对交叉耦合的NMOS晶体管实现电压转换，其中源极与全局位线直接或间接耦合，并且其漏极与本地位直接或间接耦合线。

40. 发明授权

US07046017B1 Full-wave rectifier for capacitance measurements 有权
标题翻译：全波整流电容测量
公开(公告)号：US07046017B1
公开(公告)日：2006-05-16
申请号：US11216754
申请日：2005-08-30
申请人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
发明人： Robert J. Drost , Ronald Ho , Ivan E. Sutherland
IPC分类号： G01R27/26 , G01N27/22
CPC分类号： G01R27/2605
摘要： One embodiment of the present invention provides an electronic circuit and method for measuring a capacitance. A signal generating mechanism generates a signal having a predefined frequency and predefined low and high voltage levels on one terminal of the capacitance. The other terminal of the capacitance is coupled to a switching mechanism. The switching mechanism is set to couple the other terminal of the capacitance to a first amplifier or a second amplifier for a portion of each signal cycle thereby full-wave rectifying a transient current flowing between the two terminals in the capacitance. Outputs of the first amplifier and the second amplifier are coupled to a current measurement mechanism for measuring the current. The capacitance is determined from the measured current. Several variations on this embodiment are provided.
摘要翻译：本发明的一个实施例提供一种用于测量电容的电子电路和方法。信号发生机构在电容的一个端子上产生具有预定频率和预定义的低和高电压电平的信号。电容的另一个端子耦合到开关机构。开关机构被设置为将电容的另一个端子耦合到每个信号周期的一部分的第一放大器或第二放大器，由此对在电容中的两个端子之间流动的瞬态电流进行全波整流。第一放大器和第二放大器的输出耦合到用于测量电流的电流测量机构。电容由测量电流确定。提供了该实施例的几个变型。

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