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31. 发明申请

US20070234162A1 Integrated Semiconductor Memory and Methods for Testing and Operating the Same 审中-公开
标题翻译：集成半导体存储器及其测试和操作方法
公开(公告)号：US20070234162A1
公开(公告)日：2007-10-04
申请号：US11677330
申请日：2007-02-21
申请人： Roland Barth
发明人： Roland Barth
IPC分类号： G06F11/00 , G01R31/28
CPC分类号： G11C29/56 , G11C29/44 , G11C29/50012 , G11C29/50016 , G11C29/56012 , G11C2029/4402 , G11C2029/5006
摘要： In the context of functional tests a check is made to ascertain whether an integrated semiconductor memory satisfies specified operating parameters. In this case, operating parameters, such as the externally applied operating frequency or the externally applied operating voltage, are varied within specific limits. Integrated semiconductor memories which function without errors within a wide variation range of the operating parameters are classified as having high quality. Integrated semiconductor memories which, by contrast, function without any errors only in narrower tolerance ranges of the operating parameters are classified as having lower quality. During production of an integrated semiconductor memory, a data bit is stored in a memory circuit, the state of the data bit specifying whether the integrated semiconductor memory is of higher or lower quality. During operation of the integrated semiconductor memory, the quality of the semiconductor memory can be established by read-out of the memory circuit.
摘要翻译：在功能测试的上下文中，检查集成半导体存储器是否满足指定的操作参数。在这种情况下，诸如外部施加的工作频率或外部施加的工作电压的操作参数在特定限度内变化。在操作参数的宽变化范围内无差错地运行的集成半导体存储器被分类为具有高质量。相比之下，仅在操作参数的较窄公差范围内没有任何错误地起作用的集成半导体存储器被分类为具有较低的质量。在集成半导体存储器的制造期间，将数据位存储在存储器电路中，数据位的状态指定集成半导体存储器是高质量还是低质量。在集成半导体存储器的操作期间，可以通过读出存储器电路来建立半导体存储器的质量。

32. 发明授权

US06788421B2 Arrangements for coherence topographic ray tracing on the eye 失效
标题翻译：在眼睛上进行相干地形光线跟踪的安排
公开(公告)号：US06788421B2
公开(公告)日：2004-09-07
申请号：US10167130
申请日：2002-06-10
申请人： Adolf Friedrich Fercher , Roland Barth
发明人： Adolf Friedrich Fercher , Roland Barth
IPC分类号： G01B902
CPC分类号： A61B3/113 , A61B3/107 , G01B9/02029 , G01B9/02077 , G01B9/02091
摘要： Topographic measurement of eye structures based on short coherence interferometry is the subject of the invention. The problem occurring in this connection is that longitudinal and transverse eye movements during signal registration lead to errors in the measured structure. The influences of longitudinal eye movements are compensated in that the reference beam, independent from the measurement beam, is directed to the corneal vertex and is reflected at the latter. The influences of longitudinal eye movements are minimized in that the transverse position of the eye is monitored by means of a direction-dependent registration of the light reflected at the corneal vertex by means of a diode array or a four-quadrant diode and transverse misalignment is detected and compensated.
摘要翻译：基于短相干干涉测量的眼睛结构的地形测量是本发明的主题。在这方面出现的问题是在信号配准期间的纵向和横向眼睛运动导致测量结构中的误差。补偿了纵向眼动的影响，因为独立于测量光束的参考光束被引导到角膜顶点并被反射。通过借助于二极管阵列或四象限二极管在角膜顶点处反射的光的方向依赖对准来监测眼睛的横向位置，并且横向不对准是纵向眼睛运动的影响最小化检测和补偿。

33. 发明授权

US06556496B2 Semiconductor configuration with optimized refresh cycle 有权
公开(公告)号：US06556496B2
公开(公告)日：2003-04-29
申请号：US09941902
申请日：2001-08-29
申请人： Alexander Benedix , Roland Barth , Stephan Grosse , Reinhard Dueregger
发明人： Alexander Benedix , Roland Barth , Stephan Grosse , Reinhard Dueregger
IPC分类号： G11C700
CPC分类号： G11C11/406
摘要： A semiconductor configuration is described and has a temperature sensor, which measures a temperature of a semiconductor module. The measured temperature is provided to a control unit, so that the control unit can adapt a refresh cycle in the semiconductor module to the retention time corresponding to the measured temperature.

34. 发明授权

US08144755B2 Method and apparatus for determining a skew 有权
标题翻译：用于确定偏斜的方法和装置
公开(公告)号：US08144755B2
公开(公告)日：2012-03-27
申请号：US11947339
申请日：2007-11-29
申请人： Michael Bruennert , Christoph Bilger , Peter Gregorius , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Michael Bruennert , Christoph Bilger , Peter Gregorius , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： H04B3/46
CPC分类号： H04L25/03878 , H04L1/0047 , H04L1/0057 , H04L1/20
摘要： The invention provides a method and an apparatus for determining a skew of each data bit of an encoded data word received by a receiver via an interface from a transmitter comprising the steps of performing an error check and correction of the received and sampled encoded data word to calculate an error corrected encoded data word corresponding to the encoded data word transmitted by the transmitter, and correlating a sequence of error corrected encoded data words with the sampled encoded data words to determine a skew of each data bit of said received encoded data words.
摘要翻译：本发明提供了一种用于确定接收机经由来自发射机的接口接收的编码数据字的每个数据位的偏斜的方法和装置，包括以下步骤：对所接收和采样的编码数据字执行错误检查和校正，计算对应于由发送器发送的编码数据字的纠错编码数据字，并将纠错编码数据字序列与采样编码数据字进行相关，以确定所接收编码数据字的每个数据位的偏斜。

35. 发明授权

US07920433B2 Method and apparatus for storage device with a logic unit and method for manufacturing same 有权
标题翻译：具有逻辑单元的存储装置的方法和装置及其制造方法
公开(公告)号：US07920433B2
公开(公告)日：2011-04-05
申请号：US11971819
申请日：2008-01-09
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： G11C7/06
CPC分类号： G11C7/1006
摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.
摘要翻译：涉及包括多个存储器单元的存储设备的方法和装置，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元和第二数据路径，以及逻辑单元。逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。另外，提供了一种用于制造存储器件的方法。

36. 发明申请

US20110034045A1 Stacking Technique for Circuit Devices 审中-公开
标题翻译：电路器件堆叠技术
公开(公告)号：US20110034045A1
公开(公告)日：2011-02-10
申请号：US12536854
申请日：2009-08-06
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： H01R12/00 , H05K1/00
CPC分类号： H01R31/06 , H01L25/105 , H01L2224/81141 , H01L2224/81191 , H01L2225/1058 , H01L2225/1082 , H01L2225/1094 , H01R12/714 , H01R13/2421
摘要： Stackable circuit devices include mechanical and electrical connection elements that are optionally disengageable and disconnectable. The mechanical connection elements comprise pairs of complementary male and female plug-in engagement elements respectively arranged at opposite matching positions on top and bottom faces of each device package. The male and female plug-in engagement elements provide a mutual plug-in engagement. The electrical connection elements comprise a plurality of first and second complementary contact elements respectively arranged in opposite and matching positions on either the top or bottom face of each device package. When the circuit devices are stacked, the first contact elements are respectively configured to provide an electrical connection to a complementary matching second contact element of an adjacently plugged in circuit device. Some of the stackable circuit devices may accommodate an integrated memory die or chip and others of the stackable circuit devices may include line routing and distribution blocks.
摘要翻译：可堆叠电路器件包括机械和电连接元件，其可任选地可分离和可断开。机械连接元件包括分别布置在每个器件封装的顶面和底面上的相对匹配位置的成对的互补的凸形和阴插入接合元件。男性和女性插入式接合元件提供相互插件接合。电连接元件包括多个第一和第二互补触点元件，其分别布置在每个器件封装的顶面或底面上的相对位置和匹配位置。当电路器件堆叠时，第一接触元件分别构造成提供与相邻插入电路器件的互补匹配的第二接触元件的电连接。可堆叠电路设备中的一些可以容纳集成存储器管芯或芯片，并且可堆叠电路器件中的其他可以包括线路布线和分配块。

37. 发明申请

US20090267678A1 Integrated Circuit with Improved Data Rate 审中-公开
标题翻译：具有改进数据速率的集成电路
公开(公告)号：US20090267678A1
公开(公告)日：2009-10-29
申请号：US12109550
申请日：2008-04-25
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： H03K17/16
CPC分类号： H03K19/0005 , H03K19/017545 , H04L25/0278
摘要： An integrated circuit includes: a terminal for outputting data, a driver for providing the data to the terminal, and a switch for selectively connecting/disconnecting the driver to the terminal. The disconnection of the driver reduces the capacitive load on the connection between the terminal and driver, thus reducing limitations on data rate from factors such as data reflections that reduce signal quality. Selective connection/disconnection allows the driver to be reconnected to the terminal only when needed.
摘要翻译：集成电路包括：用于输出数据的终端，用于向终端提供数据的驱动器，以及用于选择性地将驱动器连接/断开到终端的开关。驱动器的断开减少了终端和驱动器之间的连接上的容性负载，从而减少了数据速率对诸如数据反射等因素的限制，降低了信号质量。选择性连接/断开允许驱动程序只在需要时重新连接到终端。

38. 发明申请

US20090175100A1 METHOD AND APPARATUS FOR STORAGE DEVICE WITH A LOGIC UNIT AND METHOD FOR MANUFACTURING SAME 有权
标题翻译：具有逻辑单元的存储装置的方法和装置及其制造方法
公开(公告)号：US20090175100A1
公开(公告)日：2009-07-09
申请号：US11971819
申请日：2008-01-09
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： G11C7/10
CPC分类号： G11C7/1006
摘要： Method and apparatus that relate to a storage device comprising a plurality of memory cells, an interface device configured to connect the storage device to a host system and configured to transmit signals to read and write data from the host system to the memory cells via a first and second data path, and a logic unit. The logic unit is configured to read and write data from the plurality of memory cells via the second data path, and configured to perform logic operations on data stored in the plurality of memory cells. When performing read and write operations, the first data path excludes the logic unit, and the second data path includes the logic unit. Furthermore, the logic unit is communicatively coupled between the interface device and the plurality of memory cells. Additionally, a method for manufacturing the memory device is provided.
摘要翻译：涉及包括多个存储器单元的存储设备的方法和设备，接口设备，被配置为将存储设备连接到主机系统，并且被配置为经由第一个存储器单元将数据从主机系统读取和写入到存储器单元和第二数据路径，以及逻辑单元。逻辑单元被配置为经由第二数据路径从多个存储器单元读取和写入数据，并且被配置为对存储在多个存储器单元中的数据执行逻辑运算。当执行读和写操作时，第一数据路径排除逻辑单元，第二数据路径包括逻辑单元。此外，逻辑单元通信地耦合在接口设备和多个存储器单元之间。另外，提供了一种用于制造存储器件的方法。

39. 发明申请

US20090150710A1 Memory System With Extended Memory Density Capability 有权
标题翻译：具有扩展内存密度能力的内存系统
公开(公告)号：US20090150710A1
公开(公告)日：2009-06-11
申请号：US11953694
申请日：2007-12-10
申请人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
发明人： Christoph Bilger , Peter Gregorius , Michael Bruennert , Maurizio Skerlj , Wolfgang Walthes , Johannes Stecker , Hermann Ruckerbauer , Dirk Scheideler , Roland Barth
IPC分类号： G06F5/06
CPC分类号： G06F13/4243
摘要： A system including a central processing unit, a first memory channel being configured to couple the central processing unit to a first semiconductor memory unit, wherein the first memory channel is configured to be clocked with a first clock frequency, and a second memory channel being configured to couple the central processing unit to a second semiconductor memory unit, wherein the second memory channel is configured or configurable to be clocked with a second clock frequency smaller than the first clock frequency.
摘要翻译：一种包括中央处理单元的系统，第一存储器通道被配置为将中央处理单元耦合到第一半导体存储器单元，其中第一存储器通道被配置为以第一时钟频率进行计时，并且配置第二存储器通道将所述中央处理单元耦合到第二半导体存储器单元，其中所述第二存储器通道被配置或配置为以小于所述第一时钟频率的第二时钟频率进行定时。

40. 发明授权

US06798706B2 Integrated circuit with temperature sensor and method for heating the circuit 失效
标题翻译：具有温度传感器的集成电路和加热电路的方法
公开(公告)号：US06798706B2
公开(公告)日：2004-09-28
申请号：US10352824
申请日：2003-01-28
申请人： Roland Barth , Alexander Benedix , Reinhard Düregger , Stephan Grosse
发明人： Roland Barth , Alexander Benedix , Reinhard Düregger , Stephan Grosse
IPC分类号： G11C704
CPC分类号： G01K7/01
摘要： A temperature sensor is integrated together with an integrated circuit on a chip, the sensor delivering a temperature-dependent measuring signal or at least emitting a signal when the chip temperature falls below a specific prescribed value. For such an eventuality, the chip includes a special circuit device thereon, by which a current flow is generated through a provided structure of electrical conductors that keeps the temperature of the integrated circuit above a prescribed minimum temperature.
摘要翻译：温度传感器与芯片上的集成电路集成在一起，传感器传递温度相关的测量信号，或者当芯片温度低于特定规定值时至少发出信号。对于这样的可能性，芯片包括其上的专用电路装置，通过该电路，电流通过提供的集成电路的温度高于预定的最低温度的电导体的结构产生。

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