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    • 31. 发明授权
    • Multi-hit detection in associative memories
    • 联想记忆中的多重检测
    • US07788444B2
    • 2010-08-31
    • US11609464
    • 2006-12-12
    • Michael J. LeeBao G. Truong
    • Michael J. LeeBao G. Truong
    • G06F13/00G06F13/28G11C15/00
    • G11C15/04G06F12/1027
    • Mechanisms for multiple hit (multi-hit) detection in associative memories, such as a content addressable memory (CAM), are provided. The illustrative embodiments include a hit bitline that discharges as RAM side entries of the associative memory are accessed. The hit bitline is precharged high and pulled low by a series of devices that are activated as each RAM side row is accessed. As more RAM side rows are accessed, the hit bitline drops lower in voltage. The hit bitline drives an inverter with a threshold set such that any voltage equal to or lower than the threshold indicates a multi-hit situation. Any voltage higher than the threshold indicates a single hit or “no-hit” situation. Thus, from the voltage of the hit bitline, the presence of a multi-hit condition may be detected.
    • 提供了诸如内容可寻址存储器(CAM)之类的关联存储器中多次命中(多重命中)检测的机制。 示例性实施例包括作为关联存储器的RAM侧条目进行放电的命中位线。 命中位线被预充电高,并被一系列在每个RAM侧行被访问时激活的设备拉低。 随着访问更多的RAM侧行,命中位线的电压降低。 命中位线驱动具有阈值设置的逆变器,使得等于或低于阈值的任何电压指示多重命中情况。 任何高于阈值的电压都表示单次击中或“无命中”情况。 因此,从命中位线的电压可以检测到存在多命中条件。
    • 32. 发明授权
    • Transparent multi-hit correction in associative memories
    • 联想记忆中的透明多点校正
    • US07788443B2
    • 2010-08-31
    • US11609416
    • 2006-12-12
    • Michael J. LeeVinod RamaduraiBao G. Truong
    • Michael J. LeeVinod RamaduraiBao G. Truong
    • G06F13/00G06F13/28G06F11/00G11C15/00
    • G11C15/04G06F12/1027
    • A mechanism is provided for transparent multi-hit correction in associative memories. A content associative memory (CAM) device is provided that transparently and independently executes a precise corrective action in the case of a multiple hit being detected. The wordlines of a CAM array are modified to include a valid bit storage circuit element that indicates whether or not the corresponding wordline is valid or not. In operation, if multiple hits are detected, the multiple hit is signaled to the host system and the particular entries in the CAM array corresponding to the multiple hits are invalidated by setting their associated valid bit storage circuit elements to an invalid value or clearing the value in the associated valid bit storage circuit element. Any data returned to the host system as a result of the multiple hits is invalidated in the host system in response to the signaling of the multiple hits.
    • 提供了一种用于联想记忆中的透明多点校正的机制。 提供内容关联存储器(CAM)装置,其在检测到多重命中的情况下透明地且独立地执行精确的校正动作。 CAM阵列的字线被修改为包括有效位存储电路元件,其指示对应的字线是否有效。 在操作中,如果检测到多个命中,则将多次命中信号发送到主机系统,并且通过将其相关联的有效位存储电路元件设置为无效值或清除该值来使与多次命中相对应的CAM阵列中的特定条目无效 在相关联的有效位存储电路元件中。 作为多次命中的结果返回到主机系统的任何数据在主机系统中响应于多次命中的信令而无效。
    • 35. 发明授权
    • System and method of selective row energization based on write data
    • 基于写入数据的选择性行激励的系统和方法
    • US07561489B2
    • 2009-07-14
    • US12125875
    • 2008-05-22
    • Michael J. LeeJose A. ParedesPeter J. KlimSam G. Chu
    • Michael J. LeeJose A. ParedesPeter J. KlimSam G. Chu
    • G11C8/00
    • G11C8/10
    • A system and method of selective row energization based on write data, with a selective row energization system including a storage array 102 having M rows 104 and N columns 106; an N-bit data word register 108; a uniform-detect circuit 110 responsive to a data word to generate a uniform word data bit having a first value when the data word is uniform; an M-bit uniform-detect register 112 having M uniform-detect latches 114, each being associated with one of the M rows 104 and storing the uniform word data bit for the data word stored in the associated M row 104; and an M-bit row driver device 116 responsive to the uniform word data bit for each of the M rows 104 to inhibit energization of the M rows 104 for which the uniform word data bit is the first value.
    • 一种基于写入数据的选择性行激励的系统和方法,具有包括具有M行104和N列106的存储阵列102的选择行激励系统; N位数据字寄存器108; 均衡检测电路110响应于数据字以在数据字均匀时产生具有第一值的均匀字数据位; 具有M个均匀检测锁存器114的M位均匀检测寄存器112,每个均衡检测锁存器114与M行104中的一个相关联,并存储用于存储在相关联的M行104中的数据字的统一字数据位; 以及响应于M行104中的每一个的均匀字数据位的M位行驱动器设备116,以禁止均匀字数据位为第一值的M行104的通电。
    • 36. 发明申请
    • Providing Actionable Insights Based on Physiological Responses From Viewers of Media
    • 根据媒体观众的生理反应提供可行的见解
    • US20090094629A1
    • 2009-04-09
    • US12244752
    • 2008-10-02
    • Hans C. LeeTimmie T. HongMichael J. Lee
    • Hans C. LeeTimmie T. HongMichael J. Lee
    • H04N7/16
    • H04N21/42201G06Q30/02H04H60/33H04H60/64H04N7/173H04N21/252H04N21/25866H04N21/44213H04N21/475H04N21/6582H04N21/812
    • Embodiments are described that enable remote and interactive access, navigation, and analysis of reactions from viewers to a media instance. The reactions include physiological responses, survey results, verbatim feedback, event-based metadata, and derived statistics for indicators of success and failure from the viewers. The reactions are aggregated, and an interface enables remote access and navigation of the media instance, aggregated physiological responses synchronized with the media instance, survey results, and/or verbatim feedback related to the media instance. This enables users to interactively divide, dissect, parse, and analyze the reactions as they prefer. This automation provides an automated process enabling non-experts to understand complex physiological data, and to organize presentation of complex data according to their needs so as to present conclusions as appropriate to the media instance.
    • 描述了能够进行远程和交互式访问,导航和分析从观众到媒体实例的反应的实施例。 这些反应包括生理反应,调查结果,逐字反馈,基于事件的元数据,以及来自观众成功和失败指标的派生统计数据。 反应被聚合,并且接口允许媒体实例的远程访问和导航,与媒体实例同步的聚合的生理响应,调查结果和/或与媒体实例相关的逐字反馈。 这使用户可以根据需要进行交互式分割,解剖,分析和分析反应。 这种自动化提供了一个自动化过程,使非专家能够了解复杂的生理数据,并根据需要组织复杂数据的呈现,以便根据媒体实例提出结论。
    • 38. 发明申请
    • System and Method for Detecting Viewer Attention to Media Delivery Devices
    • 用于检测查看器注意介质传送设备的系统和方法
    • US20090070798A1
    • 2009-03-12
    • US12206700
    • 2008-09-08
    • Hans C. LeeMichael J. LeeTim Hong
    • Hans C. LeeMichael J. LeeTim Hong
    • H04H60/33
    • A61B5/168A61B5/1113A61B5/16A61B5/165A61B5/6814A61B2562/0219
    • Embodiments of a system to accurately record if viewers are actually watching, listening to, interacting with, or otherwise perceiving a television, computer monitor, or other media delivery device at any given moment are described. A detector circuit is coupled to the media delivery device and configured to receive a signal transmitted from an emitter placed on the body of a user positioned proximate the media delivery device. The detector receives a signal from the emitter when the user positions him or herself in a manner that indicates that the user is watching or otherwise paying attention to the media delivery device. An attention detector processor coupled to the detector circuit and configured to determine whether the user is perceiving content provided by the media deliver device.
    • 描述了在任何给定时刻准确地记录观看者是否正在观看,收听,与电视,计算机监视器或其他媒体传送设备相互影响或以其他方式感知的系统的实施例。 检测器电路耦合到介质输送装置并且被配置为接收从放置在位于介质输送装置附近的使用者的身体上的发射器发送的信号。 当用户以指示用户正在观看或以其他方式注意媒体传送设备的方式定位他或她时,检测器从发射器接收信号。 注意检测器处理器,耦合到检测器电路并且被配置为确定用户是否感知由媒体传送设备提供的内容。
    • 40. 发明授权
    • Alignment insensitive D-cache cell
    • 对齐不敏感的D缓存单元
    • US07304352B2
    • 2007-12-04
    • US11111454
    • 2005-04-21
    • K. Paul MullerKevin A. BatsonMichael J. Lee
    • K. Paul MullerKevin A. BatsonMichael J. Lee
    • H01L29/76H01L29/94
    • G11C11/412H01L27/11H01L27/1104Y10S257/903Y10S257/904
    • A D-Cache SRAM cell having a modified design in schematic and layout that exhibits increased symmetry from the circuit schematic and the physical cell layout perspectives. That is, the SRAM cell includes two read ports and minimizes asymmetry by provisioning one read port on a true side and one on the complement side. Asymmetry is additionally minimized in layout as cross coupling on both the true and complement sides rises up one level by providing from the local interconnect level a via connection to a M1 or metallization level. Moreover, the distance between the local interconnect (MC) and the gate conductor structure (PC) has been enlarged and equalized for each of the pFETs in the cross-latched SRAM cell. As a result, the SRAM cell has been rendered insensitive to overlay (local interconnect processing too close) by maximizing this MC-PC distance.
    • 具有改进的示意图和布局设计的D缓存SRAM单元,其显示出来自电路原理图和物理单元布局视角的增加的对称性。 也就是说,SRAM单元包括两个读取端口,并且通过在真实侧提供一个读取端口和在补充端上提供一个读取端口来最小化不对称性。 通过从本地互连级别提供通向M1或金属化级别的通孔连接,通过从真实和补偿侧两者的交叉耦合上升到一个级别,不对称性在布局中另外最小化。 此外,局部互连(MC)和栅极导体结构(PC)之间的距离已经在交叉锁存SRAM单元中的每个pFET被放大和均衡。 因此,通过最大化这个MC-PC距离,SRAM单元已经对覆盖(局部互连处理太近)变得不敏感。