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    • 32. 发明申请
    • Tunable MMIC (monolithic microwave integrated circuit) waveguide resonators
    • 可调MMIC(单片微波集成电路)波导谐振器
    • US20070109078A1
    • 2007-05-17
    • US11288049
    • 2005-11-14
    • Mark KintisFlavia FongThomas WongXing Lan
    • Mark KintisFlavia FongThomas WongXing Lan
    • H01P7/00
    • H01P7/065
    • A ferroelectric loaded waveguide resonator capable of operation at microwave, millimeter-wave and higher frequencies and suitable for integration into a three-dimensional monolithic microwave integrated circuit (3D MMIC) is disclosed. The resonator includes a resonator cavity, which, in one form of the invention, is formed by two parallel metal layers and a metallized wall structure extending between the metal layers. The cavity is filled with dielectric material and includes a layer of ferroelectric material, which is used to control the resonant frequency by varying a voltage bias applied to the ferroelectric layer. The cavity includes a slot in one of the metal layers and a coupling strip formed adjacent to the slot to provide electromagnetic coupling to other components, such as a voltage controlled oscillator (VCO). The invention can also be applied to other multi-metal semiconductor or wafer level packaging technologies.
    • 公开了一种能够在微波,毫米波和更高频率下操作并且适合于集成到三维单片微波集成电路(3D MMIC)中的铁电负载波导谐振器。 谐振器包括谐振器腔,其在本发明的一种形式中由两个平行的金属层和在金属层之间延伸的金属化壁结构形成。 空腔填充有电介质材料,并且包括铁电材料层,其用于通过改变施加到铁电层的电压偏压来控制谐振频率。 空腔包括在金属层中的一个中的槽和与槽相邻形成的耦合条,以提供与其它部件(例如压控振荡器(VCO))的电磁耦合。 本发明也可应用于其他多金属半导体或晶圆级封装技术。
    • 33. 发明申请
    • 3D MMIC VCO and methods of making the same
    • 3D MMIC VCO和制作方法相同
    • US20070069824A1
    • 2007-03-29
    • US11236033
    • 2005-09-27
    • Mark KintisFlavia FongThomas WongXing Lan
    • Mark KintisFlavia FongThomas WongXing Lan
    • H03K3/03
    • H03B5/1841
    • A three dimensional (3D) microwave monolithic integrated circuit (MMIC) multi-push voltage controlled oscillator (VCO) and methods of making the same is provided. The 3D MMIC multi-push oscillator includes a plurality of matching frequency oscillators coupled to a phasing ring in substantially equidistantly spaced apart locations. A combined VCO output signal is provided at a central output connection point of the phasing ring. The central output connection point resides on a first plane. An output conductor transition has a first end coupled to the central output connection point and a second end provided as an output to the quad-push VCO. The output conductor transition extends transverse to the first plane and terminates at a second plane separated from the first plane. The multi-push oscillator can be a push-push, quad-push or N-push type VCO based on a particular implementation.
    • 提供三维(3D)微波单片集成电路(MMIC)多压电压控振荡器(VCO)及其制作方法。 3D MMIC多按钮振荡器包括多个匹配的频率振荡器,其耦合到基本上等间隔开的位置的相控环。 在相控环的中心输出连接点处提供组合的VCO输出信号。 中央输出连接点位于第一平面上。 输出导体跃迁具有耦合到中心输出连接点的第一端和作为四推压VCO的输出提供的第二端。 输出导体跃迁横向于第一平面延伸并终止于与第一平面分离的第二平面。 多按钮振荡器可以是基于特定实现的推挽式,四推式或N推式VCO。
    • 36. 发明申请
    • Integrated schottky transistor logic configuration
    • 集成肖特基晶体管逻辑配置
    • US20050062503A1
    • 2005-03-24
    • US10665645
    • 2003-09-18
    • Thomas WongRobert BechdoltPhi Thai
    • Thomas WongRobert BechdoltPhi Thai
    • H03K19/084H03K19/20
    • H03K19/0846
    • A logic gate is described that has an N-type region, which may be an N-well or N-tub, forming a cathode of one or more Schottky diodes and a collector of an NPN bipolar transistor. Accordingly, the Schottly diodes and transistor do not need to be isolated from one another, resulting in a very compact logic gate. The logic gate forms a portion of a NAND function in one embodiment. One or more Schottky diodes between the collector and base of the bipolar transistor act as a clamp to prevent the transistor from saturating. The clamp diodes can also be used to adjust the output voltage of the gate to ensure downstream transistors can be fully turned off.
    • 描述了具有N型区域的逻辑门,其可以是N阱或N形槽,形成一个或多个肖特基二极管的阴极和NPN双极晶体管的集电极。 因此,肖特基二极管和晶体管不需要彼此隔离,导致非常紧凑的逻辑门。 在一个实施例中,逻辑门形成NAND功能的一部分。 双极晶体管的集电极和基极之间的一个或多个肖特基二极管用作钳位,以防止晶体管饱和。 钳位二极管也可用于调节栅极的输出电压,以确保下游晶体管可以完全关断。