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31. 发明申请

US20060176885A1 Data processing system, method and interconnect fabric having an address-based launch governor 失效
标题翻译：具有基于地址的发射调速器的数据处理系统，方法和互连结构
公开(公告)号：US20060176885A1
公开(公告)日：2006-08-10
申请号：US11054910
申请日：2005-02-10
申请人： Benjiman Goodman , Praveen Reddy , Jeffrey Stuecheli
发明人： Benjiman Goodman , Praveen Reddy , Jeffrey Stuecheli
IPC分类号： H04L12/28
CPC分类号： G06F12/0831 , G06F12/0811 , G06F12/0813 , G06F12/0851
摘要： A data processing system includes an interconnect fabric, a protected resource having a plurality of banks each associated with a respective one of a plurality of address sets, a snooper that controls access to the resource, one or more masters that initiate requests, and interconnect logic coupled to the one or more masters and to the interconnect fabric. The interconnect logic regulates a rate of delivery to the snooper via the interconnect fabric of requests that target any one the plurality of banks of the protected resource.
摘要翻译：数据处理系统包括互连结构，受保护资源具有多个存储体，每个存储体各自与多个地址集合中的相应一个地址集相关联，控制对资源的访问的监听器，发起请求的一个或多个主站和互连逻辑耦合到一个或多个主器件和互连结构。互连逻辑通过针对受保护资源的多个组中的任一个的请求的互连结构来调节到窥探者的传送速率。

32. 发明申请

US20120203973A1 SELECTIVE CACHE-TO-CACHE LATERAL CASTOUTS 审中-公开
标题翻译：选择性高速缓存行驶路线
公开(公告)号：US20120203973A1
公开(公告)日：2012-08-09
申请号：US13445646
申请日：2012-04-12
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

33. 发明申请

US20110161587A1 PROACTIVE PREFETCH THROTTLING 有权
标题翻译：主动推荐曲线
公开(公告)号：US20110161587A1
公开(公告)日：2011-06-30
申请号：US12649548
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams
IPC分类号： G06F12/08 , G06F12/00
CPC分类号： G06F12/0862 , G06F12/0815
摘要： According to a method of data processing, a memory controller receives a plurality of data prefetch requests from multiple processor cores in the data processing system, where the plurality of prefetch load requests include a data prefetch request issued by a particular processor core among the multiple processor cores. In response to receipt of the data prefetch request, the memory controller provides a coherency response indicating an excess number of data prefetch requests. In response to the coherency response, the particular processor core reduces a rate of issuance of data prefetch requests.
摘要翻译：根据数据处理的方法，存储器控制器从数据处理系统中的多个处理器核心接收多个数据预取请求，其中多个预取负载请求包括由多处理器中的特定处理器核发出的数据预取请求核心。响应于接收到数据预取请求，存储器控制器提供指示多余数据预取请求的一致性响应。响应于一致性响应，特定处理器核心降低了数据预取请求的发布速率。

34. 发明申请

US20080052471A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT COMMUNICATION UTILIZING AN IG COHERENCY STATE 失效
标题翻译：数据处理系统和使用IG语音状态的高效通信的方法
公开(公告)号：US20080052471A1
公开(公告)日：2008-02-28
申请号：US11836965
申请日：2007-08-10
申请人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： JAMES FIELDS, JR. , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.
摘要翻译：高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元和高速缓冲存储器。高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。一致性状态字段具有多个可能的状态，包括指示地址标签有效的状态，存储位置不包含有效数据，并且存储器块可能被高速缓存在第一相干域之外。

35. 发明申请

US20060179248A1 Data processing system and method for efficient storage of metadata in a system memory 失效
标题翻译：用于在系统存储器中有效存储元数据的数据处理系统和方法
公开(公告)号：US20060179248A1
公开(公告)日：2006-08-10
申请号：US11055640
申请日：2005-02-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

36. 发明申请

US20060179247A1 Data processing system and method for efficient communication utilizing an Ig coherency state 失效
公开(公告)号：US20060179247A1
公开(公告)日：2006-08-10
申请号：US11055524
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： G06F13/28
CPC分类号： G06F12/0831 , G06F12/0813
摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit and a cache memory. The cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the address tag is valid, that the storage location does not contain valid data, and that the memory block is possibly cached outside of the first coherency domain.

37. 发明申请

US20060176906A1 Data processing system, method and interconnect fabric for selective link information allocation in a data processing system 失效
公开(公告)号：US20060176906A1
公开(公告)日：2006-08-10
申请号：US11055366
申请日：2005-02-10
申请人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
发明人： James Fields , Guy Guthrie , William Starke , Jeffrey Stuecheli
IPC分类号： H04J3/22 , H04J3/16 , H04L12/26 , H04J3/14
CPC分类号： G06F15/177 , G06F12/0831 , G06F12/0897
摘要： A data processing system includes a plurality of processing units coupled for communication by a communication link and a configuration register. The configuration register has a plurality of different settings each corresponding to a respective one of a plurality of different link information allocations. Information is communicated over the communication link in accordance with a particular link information allocation among the plurality of link information allocations determined by a respective setting of the configuration register.

38. 发明授权

US09189403B2 Selective cache-to-cache lateral castouts 有权
标题翻译：选择性高速缓存到缓存横向转义
公开(公告)号：US09189403B2
公开(公告)日：2015-11-17
申请号：US12650018
申请日：2009-12-30
申请人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
发明人： Guy L. Guthrie , William J. Starke , Jeffrey Stuecheli , Derek E. Williams , Thomas R. Puzak
IPC分类号： G06F12/00 , G06F12/08 , G06F12/12
CPC分类号： G06F12/0811 , G06F12/12
摘要： A data processing system includes first and second processing units and a system memory. The first processing unit has first upper and first lower level caches, and the second processing unit has second upper and lower level caches. In response to a data request, a victim cache line to be castout from the first lower level cache is selected, and the first lower level cache selects between performing a lateral castout (LCO) of the victim cache line to the second lower level cache and a castout of the victim cache line to the system memory based upon a confidence indicator associated with the victim cache line. In response to selecting an LCO, the first processing unit issues an LCO command on the interconnect fabric and removes the victim cache line from the first lower level cache, and the second lower level cache holds the victim cache line.
摘要翻译：数据处理系统包括第一和第二处理单元和系统存储器。第一处理单元具有第一上层和第一下层高速缓存，第二处理单元具有第二上层和下层高速缓存。响应于数据请求，选择要从第一较低级高速缓存丢弃的受害者高速缓存行，并且第一较低级高速缓存选择在执行到第二低级高速缓存的受害者高速缓存行的横向流出（LCO）基于与受害者高速缓存行相关联的置信指示，将受害者缓存行的丢弃发送到系统存储器。响应于选择LCO，第一处理单元在互连结构上发布LCO命令，并从第一低级缓存中移除受害者高速缓存行，并且第二下级缓存保存受害缓存行。

39. 发明申请

US20080091905A1 EXECUTING BACKGROUND WRITES TO IDLE DIMMS 失效
标题翻译：执行背景写入空白
公开(公告)号：US20080091905A1
公开(公告)日：2008-04-17
申请号：US11951735
申请日：2007-12-06
申请人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
发明人： Mark Brittain , Warren Maule , Gary Morrison , Jeffrey Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F13/161 , G06F13/1626
摘要： Memory modules are designed with multiple write buffers utilized to temporarily hold write data. “Write-to-buffer” operations moves write data from the memory controller to the write buffers while the memory module is busy processing read operations. Then, address-only “write” commands are later issued to write the buffered write data to the memory device. The write commands targeting idle DIMMs are issued in sequence ahead of writes targeting busy DIMMs (or soon to be busy). Moving the data via a background write-to-buffer operation increases the efficiency of the common write data channel and allows the write data bus to reach maximum bandwidth during periods of heavy read activity. The actual write operations, deferred to periods of when the negative affects of the write can be completely/mostly hidden. In periods of light read activity or when there are no reads pending, buffering data in the memory module enables the buffered data to be written in parallel across multiple memory modules simultaneously.
摘要翻译：内存模块设计有多个写入缓冲器，用于临时保存写入数据。 “写入缓冲”操作将内存控制器中的写入数据移动到写入缓冲区，同时内存模块正忙于处理读取操作。然后，随后发出仅地址的“写入”命令来将缓冲的写入数据写入存储器件。针对闲置DIMM的写命令在针对繁忙DIMM（或即将忙于）的写入之前按顺序发出。通过后台写入缓冲操作移动数据可以提高通用写入数据通道的效率，并允许写入数据总线在重读操作期间达到最大带宽。实际写入操作，延迟到写入负面影响的时期可以完全/大部分隐藏。在光读取活动期间，或者当没有读取待处理时，缓冲存储器模块中的数据使缓冲数据能够同时跨多个存储器模块并行编写。

40. 发明申请

US20080028156A1 DATA PROCESSING SYSTEM AND METHOD FOR EFFICIENT STORAGE OF METADATA IN A SYSTEM MEMORY 有权
标题翻译：数据处理系统和方法，用于在系统存储器中有效存储元数据
公开(公告)号：US20080028156A1
公开(公告)日：2008-01-31
申请号：US11836908
申请日：2007-08-10
申请人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
发明人： James Fields , Sanjeev Ghai , Warren Maule , Jeffrey Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F11/1064 , G06F12/0831
摘要： A cache coherent data processing system includes a plurality of processing units each having at least an associated cache, a system memory, and a memory controller that is coupled to and controls access to the system memory. The system memory includes a plurality of storage locations for storing a memory block of data, where each of the plurality of storage locations is sized to store a sub-block of data. The system memory further includes metadata storage for storing metadata, such as a domain indicator, describing the memory block. In response to a failure of a storage location for a particular sub-block among the plurality of sub-blocks, the memory controller overwrites at least a portion of the metadata in the metadata storage with the particular sub-block of data.
摘要翻译：高速缓存一致性数据处理系统包括多个处理单元，每个处理单元至少具有相关联的高速缓存，系统存储器和存储器控制器，其耦合到并控制对系统存储器的访问。系统存储器包括用于存储数据的存储块的多个存储位置，其中多个存储位置中的每一个被设置为存储数据的子块。系统存储器还包括用于存储描述存储器块的诸如域指示符的元数据的元数据存储。响应于多个子块中的特定子块的存储位置的故障，存储器控制器使用特定的数据子块来覆盖元数据存储器中的元数据的至少一部分。

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