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    • 32. 发明授权
    • Method and circuit for pre-emphasis equalization in high speed data communications
    • 高速数据通信中预加重均衡的方法和电路
    • US06794900B2
    • 2004-09-21
    • US10205340
    • 2002-07-24
    • Benjamim TangRichard C. Pierson
    • Benjamim TangRichard C. Pierson
    • H03K19003
    • H04L25/0286H04L25/0272H04L25/0288H04L25/03878
    • A method and circuit for pre-emphasis equalization of a high speed data communication system can be provided through the use of programmable pulse shaping. A data communication system configured with the pre-emphasis equalization circuit operates by receiving an input data stream and outputting a data stream for transmission through an interconnect or other transmission channel. The data can be passed through an output buffer configured with programmable pre-emphasis equalization, having input inverters at an input stage and output inverters at an output stage. During operation, once an input signal to the input stage transitions, for example from a low to a high state, an input signal to the output stage is configured to a full amplitude to drive the transmission channel. Once the output stage transitions to a full amplitude, the input of the output stage is configured closer to a mid-scale amplitude. The amount of amplitude change from full scale back to mid-scale determines the amount of equalization to be provided by the output buffer to the transmission channel.
    • 可以通过使用可编程脉冲整形来提供用于高速数据通信系统的预加重均衡的方法和电路。 配置有预加重均衡电路的数据通信系统通过接收输入数据流并通过互连或其他传输信道输出数据流进行传输。 数据可以通过配置有可编程预加重均衡的输出缓冲器,在输入级具有输入反相器,并在输出级输出反相器。 在操作期间,一旦输入级的输入信号转变,例如从低电平到高电平状态,到输出级的输入信号被配置为全幅度以驱动传输通道。 一旦输出级转变到一个完整的幅度,输出级的输入被配置成更接近中等幅度。 从满量程到中等刻度的幅度变化量决定了输出缓冲器向传输通道提供的均衡量。
    • 33. 发明授权
    • Methods and apparatus for a power supply
    • 电源的方法和装置
    • US09559590B2
    • 2017-01-31
    • US12043261
    • 2008-03-06
    • Benjamim TangLaura CarpenterKenneth A. Ostrom
    • Benjamim TangLaura CarpenterKenneth A. Ostrom
    • H02M3/156H02M3/158H02M1/088
    • H02M3/158H02M1/08H02M1/088H02M3/156H02M3/1584H02M2001/0048
    • Methods and apparatus for a power supply according various aspects of the present invention operate in conjunction with a voltage converter for converting an input voltage to an output voltage. For example, the converter may comprise an output controller configured to generate a control signal, a power mode controller, and an integrated power stage. The power stage may include a multiple switch segments coupled in parallel between the input voltage and the output, and a driver circuit responsive to the output controller and the power mode controller and connected to the switch segments. The driver circuit controls the switch segments according to the control signal to activate the switch segments in the switch circuit. The driver circuit also disables one or more of the switch segments according to the power mode signal to permit reduced power delivery and demand states.
    • 电源的方法和装置根据本发明的各个方面与用于将输入电压转换成输出电压的电压转换器一起工作。 例如,转换器可以包括被配置为产生控制信号的输出控制器,功率模式控制器和集成功率级。 功率级可以包括在输入电压和输出之间并联耦合的多个开关段,以及响应于输出控制器和功率模式控制器并连接到开关段的驱动器电路。 驱动器电路根据控制信号控制开关段,以激活开关电路中的开关段。 驱动器电路还根据功率模式信号禁用一个或多个开关段,以允许减少功率输送和需求状态。
    • 36. 发明授权
    • PLL/DLL dual loop data synchronization
    • PLL / DLL双循环数据同步
    • US08239579B2
    • 2012-08-07
    • US12719450
    • 2010-03-08
    • Benjamim TangScott SouthwellNicholas Robert Steffen
    • Benjamim TangScott SouthwellNicholas Robert Steffen
    • G06F15/16
    • H04J3/047H04J3/062H04J3/0685H04L7/033
    • A dual loop (PLL/DLL) data synchronization system and method for plesiochronous systems is provided. A dual loop data serializer includes a phase lock loop (PLL) and a delayed lock loop (DLL) configured with a phase shifter in the feedback path of the PLL. The dual loop serializer locks to the input of the DLL instead of the local reference. Thus, the DLL adjusts the frequency from the PLL so that it matches the desired data rate. Each loop may be optimized for jitter tolerance with the net effect generating a synthesized clean clock (due to narrow bandwidth filtering) and VCO noise suppression (due to wide bandwidth filtering). A dual loop retimer includes a dual loop serializer (PLL/DLL) and a clock recovery DLL. The retimer resets the jitter budget to meet transmission requirements for an infinite number of repeater stages.
    • 提供了一种双循环(PLL / DLL)数据同步系统和方法,用于同步系统。 双环数据串行器包括在PLL的反馈路径中配置有移相器的锁相环(PLL)和延迟锁环(DLL)。 双循环串行器锁定到DLL的输入,而不是本地引用。 因此,DLL调整来自PLL的频率,使其与期望的数据速率相匹配。 每个环路可以针对抖动容限进行优化,其净效应产生合成的干净时钟(由于窄带宽滤波)和VCO噪声抑制(由于宽带宽滤波)。 双环重定时器包括双回路串行器(PLL / DLL)和时钟恢复DLL。 重新定时器重置抖动预算以满足无限数量的中继器级的传输要求。
    • 37. 发明授权
    • Multiphase power regulator with load adaptive phase control
    • 具有负载自适应相位控制功能的多相电源调节器
    • US08193796B2
    • 2012-06-05
    • US12371835
    • 2009-02-16
    • Benjamim TangRobert T. CarrollNicholas R. SteffenRichard C. Pierson
    • Benjamim TangRobert T. CarrollNicholas R. SteffenRichard C. Pierson
    • G05F1/00
    • H02M3/1584H02M2001/0012
    • Disclosed is a power regulator for providing precisely regulated power to a microelectronic device such as a microprocessor. Improved power regulation is accomplished by optimizing the power efficiency of the power regulator. In particular, in a multiphase system, the number of active phases is increased or decreased to achieve optimum power efficiency. The multiphase voltage regulator adapts the operating mode to maximize efficiency as the load current demand of the load device changes by adjusting the number of active phases to maximize efficiency. The total value of current provided by the regulator and the total number of active phases is determined, the total number of active phases is compared with the number of active phases required to provide the total value of current at maximum efficiency; and the number of active phases is adjusted to provide the total value of current at maximum efficiency.A current sense circuit senses the current at each phase, a summing circuit coupled to the output of the current sense circuit provides the total current value of all the measured phases, a circuit coupled to the output of the summing circuit provides the time averaged total current value to a threshold detecting circuit that determines the number of phases at which the voltage regulator should be operating for maximum efficiency, and a circuit for comparing the number of phases that are operating to the number of phases at which the voltage regulator should be operating adjusts the number of active phases to the number of phases at which the voltage regulator should be operating for maximum efficiency.
    • 公开了一种功率调节器,用于向诸如微处理器的微电子器件提供精确调节的功率。 通过优化功率调节器的功率效率来实现改进的功率调节。 特别地,在多相系统中,活性相的数量增加或减少以达到最佳功率效率。 当负载设备的负载电流需求通过调节活动相数量来最大化效率而改变时,多相电压调节器可以适应操作模式以最大化效率。 确定调节器提供的电流总值和有效相的总数,将有效相的总数与最大效率提供电流总值所需的有效相数进行比较; 并且调整活动相的数量以提供最大效率的电流总值。 电流感测电路感测每相的电流,耦合到电流检测电路的输出的求和电路提供所有测量相位的总电流值,耦合到求和电路的输出的电路提供时间平均总电流 值到阈值检测电路,其确定电压调节器应该在最大效率下操作的相位数,以及用于将正在操作的相位数与用于调节电压的相位数进行比较的电路进行调整 电压调节器应运行的相数达到最大效率的有效相数。
    • 38. 发明授权
    • Active transient response circuits, system and method for digital multiphase pulse width modulated regulators
    • 有源瞬态响应电路,数字多相脉宽调制调节器的系统和方法
    • US08134354B2
    • 2012-03-13
    • US12396975
    • 2009-03-03
    • Benjamim TangRobert T. CarrollScott W. SouthwellKenneth A. OstromRichard C. Pierson
    • Benjamim TangRobert T. CarrollScott W. SouthwellKenneth A. OstromRichard C. Pierson
    • G05F1/59
    • H02M3/1584
    • Disclosed is a multi-phase pulse width modulated voltage regulator and method in which transient voltage excursions or deviations that exceed the load line voltage by more than a predetermined amount are detected by an ATR circuit and a correction signal is applied. The correction signal is in the form of asynchronous pulses and the number of such pulses is a function of the magnitude of the voltage excursion as determined by the number of thresholds that are exceeded. Also disclosed is an adaptive voltage positioning (AVP) circuit and method for early detection of a transient event by sensing voltage changes at the load and adjusting the target voltage with pre-determined current values prior to the time that ATR event changes in the current at the load are detected. The AVP load line is pre-positioned for more precise current control. Also disclosed is an adaptive filter with adjustable frequency characteristics in response to an ATR event. Also disclosed is a pulse limiting circuit. Also disclosed is a tri-state implementation. Response to transient events is further improved with an external ATR circuit coupled to the load.
    • 公开了一种多相脉宽调制电压调节器和方法,其中通过ATR电路检测超过负载线电压超过预定量的瞬态电压偏移或偏差,并且施加校正信号。 校正信号是异步脉冲的形式,并且这样的脉冲的数量是由超过的阈值的数量确定的电压偏移的大小的函数。 还公开了一种用于通过感测负载上的电压变化来早期检测瞬态事件的自适应电压定位(AVP)电路和方法,并且在ATR事件在电流当前变化的时刻之前用预定电流值调节目标电压 检测负载。 AVP负载线预先定位,以实现更精确的电流控制。 还公开了响应于ATR事件具有可调频率特性的自适应滤波器。 还公开了一种脉冲限制电路。 还公开了三态实现。 外部ATR电路耦合到负载,进一步提高对瞬态事件的响应。