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31. 发明申请

US20100002501A1 MRAM Device Structure Employing Thermally-Assisted Write Operations and Thermally-Unassisted Self-Referencing Operations 有权
标题翻译：采用热辅助写入操作和热辅助自我参考操作的MRAM器件结构
公开(公告)号：US20100002501A1
公开(公告)日：2010-01-07
申请号：US12168671
申请日：2008-07-07
申请人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
发明人： Rainer Leuschner , Ulrich Klostermann , Richard Ferrant
IPC分类号： G11C11/02 , H01L21/00 , G11C7/00
CPC分类号： G11C7/04 , B82Y25/00 , B82Y40/00 , G11C11/16 , G11C11/1675 , H01F10/3254 , H01F10/3272 , H01F41/307 , H01L27/228 , H01L43/08 , H01L43/12
摘要： A thermally-assisted MRAM structure which is programmable at a writing mode operating temperature is presented and includes an anti-ferromagnet, an artificial anti-ferromagnet, a barrier layer, and a free magnetic layer. The anti-ferromagnet is composed of a material having a blocking temperature Tb which is lower than the writing mode operating temperature of the magnetic random access memory structure. The artificial anti-ferromagnet is magnetically coupled to the anti-ferromagnet, and includes first and second magnetic layers, and a coupling layer interposed therebetween, the first and second magnetic layers having different Curie point temperatures. The barrier layer is positioned to be between the second magnetic layer and the free magnetic layer.
摘要翻译：提出了一种在写入模式工作温度下可编程的热辅助MRAM结构，其包括反铁磁体，人造抗铁磁体，阻挡层和自由磁性层。抗铁磁体由具有比磁性随机存取存储器结构的写入模式工作温度低的阻挡温度Tb的材料构成。人造抗铁磁体磁耦合到抗铁磁体，并且包括第一和第二磁性层以及插入其间的耦合层，第一和第二磁性层具有不同的居里点温度。阻挡层被定位在第二磁性层和自由磁性层之间。

32. 发明授权

US07212432B2 Resistive memory cell random access memory device and method of fabrication 有权
标题翻译：电阻式存储单元随机存取存储器件及其制造方法
公开(公告)号：US07212432B2
公开(公告)日：2007-05-01
申请号：US10955837
申请日：2004-09-30
申请人： Richard Ferrant , Daniel Braun
发明人： Richard Ferrant , Daniel Braun
IPC分类号： G11C11/00
CPC分类号： H01L27/228 , G11C8/14 , G11C11/15 , G11C2213/79 , H01L29/785
摘要： A resistive memory cell random access memory device and method for fabrication. In one embodiment, the invention relates to a resistive memory cell random access memory device comprising a plurality of first current lines; a plurality of second current lines; a plurality of third current lines being formed as split current lines; and an array of resistive memory cells arranged in columns defined by said first current lines and rows defined by said third current lines, each resistive memory cell including a resistive memory element and an access transistor connected in series, each memory cell being connected between one of said first current lines and a reference potential, wherein said access transistors being FinFET-type field effect transistors, each one having two independent gates and a common floating body, and wherein each third current line being connected to one of said two independent gates of each one of the access transistors of a row of said array and being connected to one of said two independent gates of each one of the access transistors of an adjacent row of said array. It also relates to a method for its fabrication.
摘要翻译：一种电阻式存储单元随机存取存储器件及其制造方法。在一个实施例中，本发明涉及包括多条第一电流线的电阻式存储单元随机存取存储器件; 多条第二电流线; 多条第三电流线被形成为分流电流线; 以及由所述第一电流线限定的列和由所述第三电流线限定的行的电阻性存储单元的阵列，每个电阻性存储单元包括电阻性存储元件和串联连接的存取晶体管，每个存储单元连接在所述第一电流线和参考电位，其中所述存取晶体管是FinFET型场效应晶体管，每个具有两个独立的栅极和共同的浮动体，并且其中每个第三电流线连接到每个的所述两个独立栅极之一所述阵列的行的存取晶体管之一并且连接到所述阵列的相邻行的每个存取晶体管的每一个的所述两个独立栅极之一。它还涉及其制造方法。

33. 发明授权

US07161863B2 DRAM refreshment 有权
标题翻译： DRAM刷新
公开(公告)号：US07161863B2
公开(公告)日：2007-01-09
申请号：US10627955
申请日：2003-07-25
申请人： Richard Ferrant , François Jacquet
发明人： Richard Ferrant , François Jacquet
IPC分类号： G11C7/00
CPC分类号： G11C11/406
摘要： A DRAM including an array of storage elements arranged in lines and columns, and for each column: write means adapted to biasing at least a selected one of the elements to a charge level chosen from among a first predetermined high level and a second predetermined low level, combined with read circuitry adapted to determining whether the stored charge level is greater or smaller than a predetermined charge level; and isolation circuitry adapted to isolating the array from the read and/or write means, each column further including refreshment means, distinct from the read and write circuit, for increasing, beyond the first and second predetermined levels, the charge stored in a storage element.
摘要翻译：一种DRAM，包括排列成行和列的存储元件的阵列，并且用于每列：写入装置，其适于将至少一个所选元素偏置到从第一预定高电平和第二预定低电平中选择的电荷电平与读取电路组合，适于确定所存储的电荷电平是否大于或小于预定电荷电平; 以及隔离电路，其适于将阵列与读取和/或写入装置隔离，每列还包括与读取和写入电路不同的刷新装置，用于在第一和第二预定级别之外增加存储在存储元件中的电荷。

34. 发明授权

US06765405B2 Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind 失效
标题翻译：防止电压或电流尖峰的保护电路，以及使用这种保护电路的时钟电路
公开(公告)号：US06765405B2
公开(公告)日：2004-07-20
申请号：US10191089
申请日：2002-07-09
申请人： Jean-Francois Hugues , Philippe Roche , Richard Ferrant
发明人： Jean-Francois Hugues , Philippe Roche , Richard Ferrant
IPC分类号： H03K1716
CPC分类号： H03K19/00338 , H03K19/0075
摘要： Disclosed are protection circuitry, and methods of operating the same, for use with clock circuits associated with integrated circuits (ICs). According to one exemplary embodiment, the protection circuitry is operable to generate at least two intermediate clock signals as a function of a received clock signal, and process the at least two intermediate clock signals to (i) cause an output of the protection circuitry to enter a high-impedance state when the at least two intermediate clock signals are different, and (ii) generate a resultant clock signal at the output of the protection circuitry equal to the received clock signal when the at least two intermediate clock signals are identical.
摘要翻译：公开了用于与集成电路（IC）相关的时钟电路使用的保护电路及其操作方法。根据一个示例性实施例，保护电路可操作以产生作为接收到的时钟信号的函数的至少两个中间时钟信号，并处理该至少两个中间时钟信号以使（i）使保护电路的输出进入当所述至少两个中间时钟信号不同时，高阻抗状态;以及（ii）当所述至少两个中间时钟信号相同时，在所述保护电路的输出处产生等于接收到的时钟信号的合成时钟信号。

35. 发明授权

US06556092B1 Low consumption oscillator 有权
标题翻译：低功耗振荡器
公开(公告)号：US06556092B1
公开(公告)日：2003-04-29
申请号：US09627814
申请日：2000-07-28
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： H03B532
CPC分类号： H03K3/012 , H03K3/0307
摘要： A low consumption oscillator having an inverter connected to a high supply potential and to a low supply potential via two respective resistors, with the resistors formed of capacitors having strong leakages.
摘要翻译：低功耗振荡器，其具有通过两个相应的电阻器连接到高电源电位和低电源电压的反相器，电阻器由具有强泄漏的电容器形成。

36. 发明授权

US4761767A High reliability integrated circuit memory 失效
标题翻译：高可靠性集成电路存储器
公开(公告)号：US4761767A
公开(公告)日：1988-08-02
申请号：US818030
申请日：1986-01-13
申请人： Richard Ferrant
发明人： Richard Ferrant
IPC分类号： G11C29/00 , G11C29/04 , G11C7/00
CPC分类号： G11C29/785 , G11C29/832
摘要： The invention provides integrated circuit memories with repair circuits. These repair circuits allow redundant memory cell lines to be substituted for defective cell lines. The invention takes advantage of the existence of these substitution circuits for electrically, and no longer only functionally, decoupling the defective lines. A connection connects circuits for biasing the cell lines to the repair circuit of this line. When the line is repaired (i.e. neutralized) it is automatically unbiased.
摘要翻译：本发明提供具有修复电路的集成电路存储器。这些修复电路允许冗余存储器单元线代替有缺陷的细胞系。本发明利用这些替代电路的存在，这些替代电路用于电而且不再仅在功能上解耦有缺陷的线。一个连接连接用于将电池线偏置到该线路的修复电路的电路。当线路被修复（即被中和）时，它是自动无偏的。

37. 发明授权

US09490264B2 Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device 有权
标题翻译：具有通过掩埋绝缘层的半导体区域之间的接触的器件，以及用于制造所述器件的工艺
公开(公告)号：US09490264B2
公开(公告)日：2016-11-08
申请号：US12984466
申请日：2011-01-04
申请人： Carlos Mazure , Richard Ferrant
发明人： Carlos Mazure , Richard Ferrant
IPC分类号： H01L21/331 , H01L21/8222 , H01L27/12 , H01L21/74 , H01L21/84 , H01L27/108 , H01L29/732 , H01L29/78 , H01L29/786
CPC分类号： H01L27/1203 , H01L21/743 , H01L21/84 , H01L27/10802 , H01L27/10873 , H01L29/732 , H01L29/7841 , H01L29/78639
摘要： The invention relates to a semiconductor device produced on a semiconductor-on-insulator substrate that includes a thin layer of semiconductor material separated from a base substrate by a buried insulating layer, the device including a first conducting region in the thin layer, a second conducting region in the base substrate and a contact connecting the first region to the second region through the insulating layer. The invention also relates to a process for fabricating such semiconductor devices.
摘要翻译：本发明涉及一种在绝缘体上半导体衬底上制造的半导体器件，其包括通过掩埋绝缘层与基底衬底分离的半导体材料的薄层，该器件包括薄层中的第一导电区域，第二导电层区域和通过绝缘层将第一区域连接到第二区域的接触。本发明还涉及制造这种半导体器件的方法。

38. 发明授权

US09159400B2 Semiconductor memory having staggered sense amplifiers associated with a local column decoder 有权
标题翻译：具有与本地列解码器相关联的交错读出放大器的半导体存储器
公开(公告)号：US09159400B2
公开(公告)日：2015-10-13
申请号：US13422697
申请日：2012-03-16
申请人： Richard Ferrant , Gerhard Enders , Carlos Mazure
发明人： Richard Ferrant , Gerhard Enders , Carlos Mazure
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4097
CPC分类号： G11C11/4091 , G11C7/065 , G11C11/4097
摘要： A semiconductor memory having bit lines and wordlines crossing each other, a memory cell array formed by memory cells arranged in rows and columns on crossover points of the bit lines and wordlines, and sense amplifier banks arranged on opposite sides of the memory cell array. Each sense amplifier bank has staggered sense amplifiers connected to a bit line according to an interleaved arrangement whereby bit lines alternate in the direction of the wordlines between bit lines coupled to different sense amplifiers. This results in interconnect spaces parallel to the bit lines. Also, each sense amplifier bank includes a local column decoder for selecting a sense amplifier and which is staggered with the sense amplifiers and coupled to the sense amplifier by an output line running in an available interconnect space parallel to the bit lines.
摘要翻译：具有彼此交叉的位线和字线的半导体存储器，由位线和字线的交叉点上以列和列排列的存储单元形成的存储单元阵列以及布置在存储单元阵列的相对侧上的读出放大器组。每个读出放大器组具有根据交错布置连接到位线的交错读出放大器，由此位线在耦合到不同读出放大器的位线之间的字线方向上交替。这导致互连空间与位线平行。此外，每个读出放大器组包括本地列解码器，用于选择读出放大器，并与读出放大器交错，并通过在平行于位线的可用互连空间中运行的输出线耦合到读出放大器。

39. 发明授权

US09111593B2 Differential sense amplifier without dedicated precharge transistors 有权
标题翻译：差分放大器，无专用预充电晶体管
公开(公告)号：US09111593B2
公开(公告)日：2015-08-18
申请号：US13456057
申请日：2012-04-25
申请人： Richard Ferrant , Roland Thewes
发明人： Richard Ferrant , Roland Thewes
IPC分类号： G11C7/00 , G11C7/06 , G11C7/12 , G11C11/4091 , G11C11/4094
CPC分类号： G11C7/065 , G11C7/12 , G11C11/4091 , G11C11/4094
摘要： The invention relates to a differential sense amplifier for sensing data stored in a plurality of memory cells of a memory cell array, including a first CMOS inverter having an output connected to a first bit line and an input connected to a second bit line complementary to the first bit line, and a second CMOS inverter having an output connected to the second bit line and an input connected to the first bit line (BL). Each CMOS inverter includes a pull-up transistor and a pull-down transistor, with the sense amplifier having a pair of precharge transistors arranged to be respectively coupled to the first and second bit lines, to precharge the first and second bit lines to a precharge voltage. The precharge transistors are constituted by the pull-up transistors or by the pull-down transistors.
摘要翻译：本发明涉及用于感测存储在存储单元阵列的多个存储器单元中的数据的差分读出放大器，包括具有连接到第一位线的输出的第一CMOS反相器和连接到与第一位线互补的第二位线的输入第一位线和第二CMOS反相器，其具有连接到第二位线的输出和连接到第一位线（BL）的输入。每个CMOS反相器包括一个上拉晶体管和一个下拉晶体管，其中读出放大器具有一对分别耦合到第一和第二位线的预充电晶体管，以将第一和第二位线预充电到预充电电压。预充电晶体管由上拉晶体管或下拉晶体管构成。

40. 发明授权

US08654602B2 Pseudo-inverter circuit on SeOI 有权
标题翻译： SeOI上的伪逆变电路
公开(公告)号：US08654602B2
公开(公告)日：2014-02-18
申请号：US13495632
申请日：2012-06-13
申请人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
发明人： Carlos Mazure , Richard Ferrant , Bich-Yen Nguyen
IPC分类号： G11C8/00
CPC分类号： G11C8/08 , G11C11/4085 , G11C2211/4016
摘要： A circuit made on a semiconductor-on-insulator substrate. The circuit includes a first transistor having a first channel, a second transistor having a second channel, with the transistors provided in serial association between first and second terminals for applying a power supply potential, each of the transistors comprising a drain region and a source region in the thin layer, a channel extending between the source region and the drain region, and a front control gate located above the channel. Each transistor has a back control gate formed in the base substrate below the channel of the transistor and capable of being biased in order to modulate the threshold voltage of the transistor. At least one of the transistors is configured for operating in a depletion mode under the action of a back gate signal which will sufficiently modulate its threshold voltage.
摘要翻译：在绝缘体上半导体衬底上制成的电路。该电路包括具有第一通道的第一晶体管，具有第二通道的第二晶体管，晶体管以第一和第二端子串联连接的方式提供，以施加电源电位，每个晶体管包括漏极区域和源极区域在薄层中，在源极区域和漏极区域之间延伸的沟道以及位于沟道上方的前部控制栅极。每个晶体管具有形成在晶体管的沟道下方的基底衬底中的背控制栅极，并且能够被偏置以便调制晶体管的阈值电压。晶体管中的至少一个被配置为在充分调制其阈值电压的背栅信号的作用下以耗尽模式工作。

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