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31. 发明申请

US20070094480A1 SYSTEM AND METHOD FOR MEMORY ARRAY ACCESS WITH FAST ADDRESS DECODER 有权
标题翻译：用于快速地址解码器的存储器阵列访问的系统和方法
公开(公告)号：US20070094480A1
公开(公告)日：2007-04-26
申请号：US11552817
申请日：2006-10-25
申请人： Ravindraraj Ramaraju , David Bearden , Prashant Kenkare
发明人： Ravindraraj Ramaraju , David Bearden , Prashant Kenkare
IPC分类号： G06F9/34
CPC分类号： G06F9/355 , G06F9/345
摘要： A method includes storing a first transaction entry to a first software configurable storage location, storing a second transaction entry to a second software configurable storage location, determining that a first transaction indicated by the first transaction entry has occurred, determining that a second transaction indicated by the second transaction entry has occurred subsequent to the first transaction, and, in response to determining that the first transaction occurred and the second transaction occurred, storing at least one transaction attribute captured during at least one clock cycle subsequent to the second transaction. The first and second software configurable storage locations may be located in a trace buffer, where the at least one transaction attribute is stored to the trace buffer and overwrites the first and second transaction attributes. Each transaction entry may include a dead cycle field, a consecutive transaction requirement field, and a last entry field.
摘要翻译：一种方法包括将第一交易条目存储到第一软件可配置存储位置，将第二交易条目存储到第二软件可配置存储位置，确定由第一交易条目指示的第一交易已经发生，确定由第一交易条目指示的第二交易第二交易条目已经在第一交易之后发生，并且响应于确定第一交易发生和第二交易发生，存储在第二交易之后的至少一个时钟周期期间捕获的至少一个交易属性。第一和第二软件可配置存储位置可以位于跟踪缓冲器中，其中至少一个事务属性被存储到跟踪缓冲器并且覆盖第一和第二事务属性。每个交易条目可以包括死循环字段，连续交易需求字段和最后输入字段。

32. 发明授权

US07200020B2 Storage element with clear operation and method thereof 失效
标题翻译：具有清晰操作的存储元件及其方法
公开(公告)号：US07200020B2
公开(公告)日：2007-04-03
申请号：US11215655
申请日：2005-08-30
申请人： Ravindraraj Ramaraju , Prashant U. Kenkare
发明人： Ravindraraj Ramaraju , Prashant U. Kenkare
IPC分类号： G11C15/00
CPC分类号： G11C7/20
摘要： A storage device and a method in the storage element, where the storage element has a first data storage node and a second data storage node and where the first data storage node is coupled to a bit line via a first pass transistor and where the second data storage node is coupled to a complementary bit line via a second pass transistor, is provided. The method includes performing a clear operation on the first data storage node and the second data storage node by providing a clear signal to a first clear transistor coupled to the first data storage node and a second clear transistor coupled to the second data storage node.
摘要翻译：存储装置和存储元件中的方法，其中所述存储元件具有第一数据存储节点和第二数据存储节点，并且其中所述第一数据存储节点经由第一传输晶体管耦合到位线，并且其中所述第二数据存储节点通过第二传输晶体管耦合到互补位线。该方法包括通过向耦合到第一数据存储节点的第一清除晶体管提供清除信号，以及耦合到第二数据存储节点的第二透明晶体管，对第一数据存储节点和第二数据存储节点执行清除操作。

33. 发明申请

US20060047935A1 Data processing system having translation lookaside buffer valid bits with lock and method therefor 有权
标题翻译：具有翻译后备缓冲器有效位的数据处理系统及其锁定方法
公开(公告)号：US20060047935A1
公开(公告)日：2006-03-02
申请号：US10928399
申请日：2004-08-27
申请人： Ravindraraj Ramaraju , David Burgess , Troy Cooper , Eric Fiene , George Hoekstra
发明人： Ravindraraj Ramaraju , David Burgess , Troy Cooper , Eric Fiene , George Hoekstra
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/1027
摘要： A system (10) translates memory addresses. Processing circuitry (12) provides an effective address to a storage array (14, 16) having a plurality of stored effective addresses, each of the plurality of stored effective addresses having a corresponding pair of a lock bit and a valid bit. An output tag value and a single valid bit are provided to a comparator (18). The lock bit defines one of two predetermined classes of tasks executed by the system. The single valid bit is applicable to both of the two predetermined classes of tasks. The lock bit qualifies the clearing of the single valid bit. The comparator respectively compares the output tag value and the single valid bit with a predetermined effective address and a predetermined bit value. An output hit signal is provided when a match occurs to validate a physical address provided by a physical address array (20).
摘要翻译：系统（10）翻译存储器地址。处理电路（12）向具有多个存储的有效地址的存储阵列（14,16）提供有效地址，所述多个存储的有效地址中的每一个具有相应的一对锁定位和有效位。将输出标签值和单个有效位提供给比较器（18）。锁定位定义系统执行的两个预定任务类别之一。单个有效位适用于两个预定类别的任务。锁定位限定单个有效位的清除。比较器分别将输出标签值和单个有效位与预定的有效地址和预定位值进行比较。当发生匹配以验证由物理地址阵列（20）提供的物理地址时，提供输出命中信号。

34. 发明申请

US20050161820A1 Integrated circuit with conductive grid for power distribution 审中-公开
标题翻译：集成电路与导电电网配电
公开(公告)号：US20050161820A1
公开(公告)日：2005-07-28
申请号：US10765810
申请日：2004-01-27
申请人： Ravindraraj Ramaraju
发明人： Ravindraraj Ramaraju
IPC分类号： H01L23/48 , H01L23/528
CPC分类号： H01L23/5286 , H01L2924/0002 , H01L2924/00
摘要： A grid for a power supply distribution of cells of circuits has a plurality of subgrids in which each subgrid has continuous lines across it. Each line has an unchanging width but the widths of the lines vary from each other. The lines on the perimeter are the thickest and each line is thinner than the previous line until the middle is reached. Thus, the line or lines in the middle are the thinnest. This provides both good uniformity in supply voltage and efficient interconnect.
摘要翻译：用于电路单元的电源分配的栅格具有多个子栅格，其中每个子网格具有跨越其的连续线。每条线具有不变的宽度，但线的宽度彼此不同。周界上的线是最厚的，每条线比前一条线更薄，直到中间到达。因此，中间的线或线是最薄的。这提供了电源电压和高效互连的均匀性。

35. 发明授权

US09317087B2 Memory column drowsy control 有权
标题翻译：内存列困倦控制
公开(公告)号：US09317087B2
公开(公告)日：2016-04-19
申请号：US13689331
申请日：2012-11-29
申请人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , Jianan Yang , Mark W. Jetton , Thomas W. Liston , George P. Hoekstra , Andrew C. Russell
IPC分类号： G06F1/26 , G06F1/32
CPC分类号： G06F1/26 , G06F1/3203 , G06F1/3225 , G06F1/3275 , G06F1/3296 , Y02D10/13 , Y02D10/14 , Y02D10/172
摘要： In accordance with at least one embodiment, column level power control granularity is provided to control a low power state of a memory using a drowsy column control bit to control the low power state at an individual column level to protect the memory from weak bit failure. In accordance with at least one embodiment, a method of using a dedicated row of bit cells in a memory array is provided wherein each bit in the row controls the low power state of a respective column in the array. A special control signal is used to access the word line, and the word line is outside of the regular word line address space. A mechanism is provided to designate the weak bit column and set the control bit corresponding to that particular column to disable the drowsy/low power state for that column.
摘要翻译：根据至少一个实施例，提供列级功率控制粒度以使用昏迷列控制位来控制存储器的低功率状态，以控制单个列级的低功率状态，以保护存储器免于弱位故障。根据至少一个实施例，提供了在存储器阵列中使用专用行位单元的方法，其中行中的每个位控制阵列中相应列的低功率状态。使用特殊的控制信号来访问字线，字线在常规字线地址空间之外。提供了一种机制来指定弱位列，并设置与该特定列相对应的控制位以禁用该列的困倦/低功率状态。

36. 发明授权

US09225337B2 Temperature threshold circuit with hysteresis 有权
标题翻译：具有迟滞的温度阈值电路
公开(公告)号：US09225337B2
公开(公告)日：2015-12-29
申请号：US14191684
申请日：2014-02-27
申请人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
发明人： Perry H. Pelley , George P. Hoekstra , Ravindraraj Ramaraju
IPC分类号： G01K1/02 , H03K21/10 , G01K7/00 , H03K21/38 , G01K13/00
CPC分类号： H03K21/10 , G01K1/028 , G01K3/005 , G01K7/32 , G01K13/002 , H03K21/38
摘要： A circuit for determining a threshold indication of temperature with respect to a threshold temperature. The circuit includes a timer circuit and a temperature sensor circuit having an counter whose output has a relationship to temperature. At the end of a period determined by the timer circuit, a comparator circuit compares the count of the counter with an indication of the threshold temperature to determine a state of the threshold indication. In response to a change in state of the threshold indication, the circuit changes one of the count time or the counter output's relationship to temperature to provide a hysteresis for the threshold indication.
摘要翻译：一种用于确定相对于阈值温度的温度阈值指示的电路。电路包括定时器电路和具有计数器的温度传感器电路，其计数器的输出与温度有关。在由定时器电路确定的周期结束时，比较器电路将计数器的计数与阈值温度的指示进行比较，以确定阈值指示的状态。响应于阈值指示的状态改变，电路将计数时间或计数器输出与温度的关系改变，以提供阈值指示的滞后。

37. 发明授权

US09141552B2 Memory using voltage to improve reliability for certain data types 有权
标题翻译：内存使用电压来提高某些数据类型的可靠性
公开(公告)号：US09141552B2
公开(公告)日：2015-09-22
申请号：US13736322
申请日：2013-01-08
申请人： Andrew C. Russell , Ravindraraj Ramaraju
发明人： Andrew C. Russell , Ravindraraj Ramaraju
IPC分类号： G06F12/00 , G06F12/08 , G11C11/412
CPC分类号： G06F12/0864 , G06F12/0893 , G06F2212/1032 , G11C11/4125
摘要： A method for minimizing soft error rates within caches by configuring a cache with a certain way which is more resistant to soft errors and then using this way to store modified data. In certain embodiments, the memory is made more soft error resistant by increasing a voltage across bitcells of the cache.
摘要翻译：一种通过以更强的抵抗软错误的方式配置缓存，然后使用这种方式存储修改后的数据来最大限度地减少高速缓存内的软错误率的方法。在某些实施例中，通过增加高速缓存的位单元上的电压，使存储器变得更柔软。

38. 发明授权

US09117498B2 Memory with power savings for unnecessary reads 有权
标题翻译：记忆功能，节省了不必要的读数
公开(公告)号：US09117498B2
公开(公告)日：2015-08-25
申请号：US13826427
申请日：2013-03-14
申请人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
发明人： Ravindraraj Ramaraju , George P. Hoekstra , Andrew C. Russell
IPC分类号： G11C7/08 , G11C8/12
CPC分类号： G11C7/08 , G11C8/12
摘要： A memory device includes a plurality of sense amplifiers, an array of memory cells including a first subset of memory cells, and a plurality of word lines. Each word line is coupled to each memory cell in a respective row of the memory cells and each row of the memory cells includes one memory cell of the first subset of memory cells. Each of a plurality of control word lines is coupled to a respective one of the memory cells in the first subset of memory cells and each of the memory cells in the first subset of memory cells generates a sense amplifier control signal coupled to control operation of a respective one of the plurality of sense amplifiers.
摘要翻译：存储器件包括多个读出放大器，包括存储器单元的第一子集的存储器单元阵列和多个字线。每个字线被耦合到存储器单元的相应行中的每个存储器单元，并且每行存储器单元包括存储器单元的第一子集的一个存储单元。多个控制字线中的每一个耦合到存储器单元的第一子集中的相应的一个存储器单元，并且存储器单元的第一子集中的每个存储单元产生一个读出放大器控制信号，相应的多个读出放大器之一。

39. 发明申请

US20140281291A1 Method and Apparatus for Memory Array Access 有权
标题翻译：用于存储器阵列存取的方法和装置
公开(公告)号：US20140281291A1
公开(公告)日：2014-09-18
申请号：US13831870
申请日：2013-03-15
申请人： Andrew C. Russell , Ravindraraj Ramaraju
发明人： Andrew C. Russell , Ravindraraj Ramaraju
IPC分类号： G06F12/00
CPC分类号： G06F12/00 , G06F9/34 , G06F12/0207 , G06F12/0215 , G06F12/06 , G06F2212/1028 , Y02D10/13
摘要： A method includes: receiving a first plurality of consecutive bits from a base operand, wherein a MSB of the first plurality of consecutive bits from the base operand is a LSB of a second plurality of consecutive bits from the base operand; and receiving a first plurality of consecutive bits from an offset operand, wherein a MSB of the first plurality of consecutive bits from the offset operand is a LSB of a second plurality of consecutive bits from the offset operand. The method includes summing the first plurality of consecutive bits from the base operand with the first plurality of consecutive bits from the offset operand to generate a sum value; and allowing access to one of a plurality of memory arrays and disabling access to the remainder of the plurality of memory arrays when a lesser significant bit to a MSB of the sum value equals zero.
摘要翻译：一种方法包括：从基本操作数接收第一多个连续比特，其中来自基本操作数的第一多个连续比特的MSB是来自基本操作数的第二多个连续比特的LSB; 以及从偏移操作数接收第一多个连续比特，其中来自所述偏移操作数的所述第一多个连续比特的MSB是来自所述偏移操作数的第二多个连续比特的LSB。该方法包括将来自基本操作数的第一多个连续比特与来自该偏移操作数的第一多个连续比特相加以产生和值; 并且当和值的MSB的较低有效位等于零时，允许访问多个存储器阵列中的一个并且禁止对多个存储器阵列的其余部分的访问。

40. 发明授权

US08837205B2 Multi-port register file with multiplexed data 有权
标题翻译：具有复用数据的多端口寄存器文件
公开(公告)号：US08837205B2
公开(公告)日：2014-09-16
申请号：US13483764
申请日：2012-05-30
申请人： Perry H. Pelley , Ravindraraj Ramaraju , Andrew C. Russell
发明人： Perry H. Pelley , Ravindraraj Ramaraju , Andrew C. Russell
IPC分类号： G11C11/00 , G11C11/413 , G11C11/412
CPC分类号： G11C11/413 , G11C7/1075 , G11C8/16 , G11C11/412 , G11C2207/007
摘要： A semiconductor memory storage device comprises an array of storage devices including a plurality of rows of the storage devices and a plurality of columns of the storage devices, a first plurality of write ports, a write select signal coupled to the write ports, a plurality of write port address lines coupled as input to each of the write ports, and a first plurality of word line select circuits coupled to receive an address signal and the write select signal for each of the write ports and to provide a single selected write word line signal to a respective one of the rows of the storage devices for one of the first plurality of write ports activated by the write select signal.
摘要翻译：一种半导体存储器存储装置，包括存储装置阵列，包括存储装置的多行和多列存储装置，第一多个写入端口，耦合到写入端口的写入选择信号，多个存储装置写入端口地址线作为输入耦合到每个写入端口，以及第一多个字线选择电路，其耦合以接收每个写入端口的地址信号和写入选择信号，并提供单个选定的写入字线信号到由写选择信号激活的第一多个写入端口之一的存储设备的相应行之一。

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