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31. 发明授权

US07069494B2 Application of special ECC matrix for solving stuck bit faults in an ECC protected mechanism 有权
标题翻译：在ECC保护机制中应用特殊ECC矩阵解决卡位故障
公开(公告)号：US07069494B2
公开(公告)日：2006-06-27
申请号：US10418549
申请日：2003-04-17
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
IPC分类号： H03M13/11
CPC分类号： G06F11/1064 , H03M13/13
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. In the illustrative embodiment, the ECC matrix has an odd number of bits set in each row thereof. In the case of an ECC protected mechanism such as a memory device, these properties facilitate the use of an inversion bit for correcting hard faults in the stored data. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted. Thereafter, the data is re-read from the array, and if the error was due to a hard fault (stuck bit), it will appear correct (after applying the polarity indicated by the inversion bit), since the inversion will have changed the value of the defective bit to the stuck value. The inversion bit may be part of the data itself. In this case, one of the columns in the ECC matrix corresponds to the inversion bit, and each bit in that column of the matrix is set. In the case of an ECC protected mechanism such as a system bus, once a stuck bit condition is detected, the sending device can elect to send data such that the polarity of the data for that bit is always flipped to match the logic level of the stuck value on the wire. This approach allows for full single-bit correct, double-bit detect even in the presence of a stuck bit.
摘要翻译：一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位纠错和（N-1）位错误检测。在说明性实施例中，ECC矩阵在其每行中设置奇数位。在诸如存储器件的ECC保护机制的情况下，这些属性有利于使用反转位来校正所存储的数据中的硬故障。当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。此后，数据从阵列重新读取，如果错误是由于硬故障（卡位）引起的，则会显示正确的（应用反转位指示的极性后），因为反转将会改变有缺陷位的值到卡住值。反转位可能是数据本身的一部分。在这种情况下，ECC矩阵中的列之一对应于反转比特，矩阵的该列中的每个比特被设置。在诸如系统总线的ECC保护机制的情况下，一旦检测到卡位状态，发送设备就可以选择发送数据，使得该位的数据的极性总是被翻转以匹配在线上卡住了值。这种方法允许完全单位正确，双位检测，即使存在卡位。

32. 发明授权

US07103721B2 Cache allocation mechanism for biasing subsequent allocations based upon cache directory state 失效
标题翻译：缓存分配机制，用于基于缓存目录状态偏置后续分配
公开(公告)号：US07103721B2
公开(公告)日：2006-09-05
申请号：US10425459
申请日：2003-04-28
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke , Jeffrey Adam Stuecheli
IPC分类号： G06F12/12
CPC分类号： G06F12/0891 , G06F12/0817
摘要： An improved method and apparatus for selecting invalid members as victims in a least recently used cache system. An invalid cache line selection unit has an input connected to a cache directory and an output connected to a most recently used update logic. In response to a miss in the cache, an invalid cache line is identified from information in the cache directory by the invalid cache line selection unit. This invalid cache line is updated to be the next victim by the most recently used update logic, rather than attempting to override the current victim selection by a least recently used victim selection logic. The next victim also may be selected in response to a cache hit in which information from the cache directory also is read.
摘要翻译：一种用于在最近最少使用的缓存系统中选择无效成员作为受害者的改进的方法和装置。无效的高速缓存线选择单元具有连接到高速缓存目录的输入和连接到最近使用的更新逻辑的输出。响应于高速缓存中的未命中，通过无效高速缓存线选择单元从高速缓存目录中的信息识别无效的高速缓存行。该无效高速缓存行被最新使用的更新逻辑更新为下一个受害者，而不是尝试通过最近最少使用的受害者选择逻辑覆盖当前的受害者选择。还可以响应于其中读取来自高速缓存目录的信息的缓存命中来选择下一个受害者。

33. 发明授权

US06996679B2 Cache allocation mechanism for saving multiple elected unworthy members via substitute victimization and imputed worthiness of multiple substitute victim members 有权
标题翻译：缓存分配机制，通过替代受害和多个替代受害者成员的估算值来保存多个选举不合格的成员
公开(公告)号：US06996679B2
公开(公告)日：2006-02-07
申请号：US10425444
申请日：2003-04-28
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F12/12
CPC分类号： G06F12/128 , G06F12/125 , G06F12/126
摘要： A method and apparatus in a data processing system for protecting against displacement of two types of cache lines using a least recently used cache management process. A first member in a class of cache lines is selected as a first substitute victim. The first substitute victim is unselectable by the least recently used cache management process, and the second substitute victim is associated with a selected member in the class of cache lines. A second member in the class of cache lines is selected as a second substitute victim. The second victim is unselectable by the least recently used cache management process, and the second substitute victim is associated with the selected member in the class of cache lines. One of the first or second substitute victims are replaced in response to a selection of the selected member as a victim when a cache miss occurs, wherein the selected member remains in the class of cache lines.
摘要翻译：一种数据处理系统中的方法和装置，用于使用最近最少使用的高速缓存管理过程来防止两种类型的高速缓存行的移位。选择一类缓存行中的第一个成员作为第一个替代受害者。第一个替代受害者不被最近使用的缓存管理进程选择，第二个替代受害者与缓存行类中的选定成员关联。选择缓存行类别中的第二个成员作为第二个替代受害者。第二个受害者不被最近使用的缓存管理进程选择，第二个替代受害者与缓存行类中的选定成员关联。当高速缓存未命中发生时，响应于所选择的成员作为受害者的选择来替换第一或第二替代受害者中的一个，其中所选择的成员保留在高速缓存行类中。

34. 发明授权

US07272773B2 Cache directory array recovery mechanism to support special ECC stuck bit matrix 失效
标题翻译：缓存目录数组恢复机制，支持特殊ECC卡位矩阵
公开(公告)号：US07272773B2
公开(公告)日：2007-09-18
申请号：US10418546
申请日：2003-04-17
申请人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
发明人： Robert Alan Cargnoni , Guy Lynn Guthrie , Kirk Samuel Livingston , William John Starke
IPC分类号： G11C29/00 , H03M13/00
CPC分类号： G06F12/0802 , G06F11/1064
摘要： A method of correcting an error in an ECC protected mechanism of a computer system, such as a cache or system bus, by applying data with a number of bits N to an error correction code (ECC) matrix to yield an error detection syndrome, wherein the ECC matrix has a plurality of rows and columns with a given column corresponding to a respective one of the data bits, and selected bits are set in the ECC matrix along each column and each row such that encoding for the ECC matrix allows N-bit error correction and (N−1)-bit error detection. When an error is detected and after it is corrected, the corrected data is inverted and then rewritten to the cache array. The corresponding inversion bit for this entry is accordingly set to indicate that the data as currently stored is inverted.
摘要翻译：一种通过将具有多个位N的数据应用于纠错码（ECC）矩阵来校正诸如高速缓存或系统总线的计算机系统的ECC保护机制中的错误的方法，以产生错误检测综合征，其中 ECC矩阵具有多个行和列，给定列对应于相应的一个数据位，并且所选择的位在每个列和每行的ECC矩阵中被设置，使得对于ECC矩阵的编码允许N位纠错和（N-1）位错误检测。当检测到错误并且在其被校正之后，校正的数据被反转，然后被重写到高速缓存阵列。因此，该条目的相应的反转位被设置为指示当前存储的数据被反转。

35. 发明申请

US20080140943A1 System and Method for Completing Full Updates to Entire Cache Lines Stores with Address-Only Bus Operations 有权
标题翻译：完整的完整更新的系统和方法完整的缓存行存储仅地址总线操作
公开(公告)号：US20080140943A1
公开(公告)日：2008-06-12
申请号：US12034769
申请日：2008-02-21
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Hugh Shen , Derek Edward Williams
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0804
摘要： A method and processor system that substantially eliminates data bus operations when completing updates of an entire cache line with a full store queue entry. The store queue within a processor chip is designed with a series of AND gates connecting individual bits of the byte enable bits of a corresponding entry. The AND output is fed to the STQ controller and signals when the entry is full. When full entries are selected for dispatch to the RC machines, the RC machine is signaled that the entry updates the entire cache line. The RC machine obtains write permission to the line, and then the RC machine overwrites the entire cache line. Because the entire cache line is overwritten, the data of the cache line is not retrieved when the request for the cache line misses at the cache or when data goes state before write permission is obtained by the RC machine.
摘要翻译：一种方法和处理器系统，其在完成具有完整存储队列条目的整个高速缓存行的更新时基本上消除数据总线操作。处理器芯片内的存储队列设计有连接相应条目的字节使能位的各个位的一系列与门。 AND输出被馈送到STQ控制器，并在条目已满时发出信号。当选择完整条目以发送到RC机器时，RC机器发出信号，表示该条目更新整个高速缓存行。 RC机器获得线路的写入权限，然后RC机器覆盖整个高速缓存行。由于整个高速缓存线被覆盖，当缓存线的请求在高速缓存中丢失或数据在RC写入权限获得之前状态时，不会检索高速缓存行的数据。

36. 发明授权

US06910062B2 Method and apparatus for transmitting packets within a symmetric multiprocessor system 失效
标题翻译：用于在对称多处理器系统内传输分组的方法和装置
公开(公告)号：US06910062B2
公开(公告)日：2005-06-21
申请号：US09918812
申请日：2001-07-31
申请人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： H04L12/42 , G06F15/17 , G06F15/16
CPC分类号： G06F15/17
摘要： The symmetric multiprocessor system includes multiple processing nodes, with multiple agents at each node, connected to each other via an interconnect. A request transaction is initiated by a master agent in a master node to all receiving nodes. A write counter number is generated for associating with the request transaction. The master agent then waits for a combined response from the receiving nodes. After the receipt of the combined response, a data packet is sent from the master agent to all intended one of the receiving nodes according to the combined response. After the data packet has been sent, the master agent in the master node is ready to send another request transaction along with a new write counter number, without the necessity of waiting for an acknowledgement from the receiving node.
摘要翻译：对称多处理器系统包括多个处理节点，每个节点具有多个代理，通过互连彼此连接。请求事务由主节点中的主代理发起到所有接收节点。生成用于与请求事务相关联的写计数器号。主代理然后等待来自接收节点的组合响应。在接收到组合响应之后，根据组合的响应，将数据分组从主代理发送到所有预期的接收节点。在发送数据分组之后，主节点中的主代理准备好发送另一请求事务以及新的写计数器号，而不需要等待来自接收节点的确认。

37. 发明授权

US06671712B1 Multi-node data processing system having a non-hierarchical interconnect architecture 有权
标题翻译：具有非分层互连架构的多节点数据处理系统
公开(公告)号：US06671712B1
公开(公告)日：2003-12-30
申请号：US09436898
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1516
CPC分类号： G06F13/4217
摘要： A data processing system includes a plurality of nodes, which each contain at least one agent, and data storage accessible to agents within the nodes. The plurality of nodes are coupled by a non-hierarchical interconnect including multiple non-blocking uni-directional address channels and at least one uni-directional data channel. The agents, which are each coupled to and snoop transactions on all of the plurality of address channels, can only issue transactions on an associated address channel. The uni-directional channels employed by the present non-hierarchical interconnect architecture permit high frequency pumped operation not possible with conventional bi-directional shared system buses. In addition, access latencies to remote (cache or main) memory incurred following local cache misses are greatly reduced as compared with conventional hierarchical systems because of the absence of inter-level (e.g., bus acquisition) communication latency. The non-hierarchical interconnect architecture also permits design flexibility in that the segment of the interconnect within each node can be independently implemented by a set of buses or as a switch, depending upon cost and performance considerations.
摘要翻译：数据处理系统包括多个节点，每个节点包含至少一个代理，以及节点内的代理可访问的数据存储。多个节点通过包括多个非阻塞单向地址信道和至少一个单向数据信道的非分层互连来耦合。在所有多个地址信道上分别耦合到并且窥探事务的代理只能在相关联的地址信道上发布事务。当前的非分层互连架构采用的单向信道允许高频抽运操作对于传统的双向共享系统总线是不可能的。另外，与传统分层系统相比，由于没有层间（例如，总线采集）通信延迟，与本地高速缓存未命中所产生的远程（高速缓存或主）存储器的访问延迟大大降低。非分层互连架构还允许设计灵活性，因为根据成本和性能考虑，每个节点内的互连部分可以由一组总线或开关单独地实现。

38. 发明授权

US06662275B2 Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with store-through data cache 有权
公开(公告)号：US06662275B2
公开(公告)日：2003-12-09
申请号：US09782578
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0848
摘要： A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

39. 发明授权

US06658556B1 Hashing a target address for a memory access instruction in order to determine prior to execution which particular load/store unit processes the instruction 失效
标题翻译：为存储器访问指令散列目标地址，以便在执行之前确定哪个特定的加载/存储单元处理该指令
公开(公告)号：US06658556B1
公开(公告)日：2003-12-02
申请号：US09364288
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steve Dodson , Guy Lynn Guthrie , Jerry Don Lewis
IPC分类号： G06F1730
CPC分类号： G06F9/3885 , G06F9/3013 , G06F9/3802 , G06F9/3814 , G06F9/3824 , G06F9/384 , G06F9/3891
摘要： A processor includes execution resources, data storage, and an instruction sequencing unit, coupled to the data storage and the execution resources, that supplies instructions within the data storage to the execution resources. The execution resources include a plurality of load-store units that each process only instructions that access data having associated addresses within a respective one of a plurality of subsets of an address space. The load-store units can have diverse hardware such that a maximum number of instructions that can be concurrently executed is different for different load-store units or such that some of the load-store units are restricted to executing certain classes of instructions.
摘要翻译：处理器包括执行资源，数据存储和与数据存储器和执行资源耦合的指令排序单元，其将数据存储器内的指令提供给执行资源。执行资源包括多个加载存储单元，每个加载存储单元仅处理在地址空间的多个子集中的相应一个子集内访问具有相关联地址的数据的指令。加载存储单元可以具有不同的硬件，使得可以并发执行的最大数量的指令对于不同的加载存储单元是不同的，或者使得一些加载存储单元被限制为执行某些类别的指令。

40. 发明授权

US06591321B1 Multiprocessor system bus protocol with group addresses, responses, and priorities 有权
标题翻译：具有组地址，响应和优先级的多处理器系统总线协议
公开(公告)号：US06591321B1
公开(公告)日：2003-07-08
申请号：US09437200
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , James Stephen Fields, Jr. , Guy Lynn Guthrie , Jody Bern Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor system bus protocol system and method for processing and handling a processor request within a multiprocessor system having a number of bus accessible memory devices that are snooping on. at least one bus line. Snoop response groups which are groups of different types of snoop responses from the bus accessible memory devices are provided. Different transfer types are provided within each of the snoop response groups. A bus master device that provides a bus master signal is designated. The bus master device receives the processor request. One of the snoop response groups and one of the transfer types are appropriately designated based on the processor request. The bus master signal is formulated from a snoop response group, a transfer type, a valid request signal, and a cache line address. The bus master signal is sent to all of the bus accessible memory devices on the cache bus line and to a combined response logic system. All of the bus accessible memory devices on the cache bus line send snoop responses in response to the bus master signal based on the designated snoop response group. The snoop responses are sent to the combined response logic system. A combined response by the combined response logic system is determined based on the appropriate combined response encoding logic determined by the designated and latched snoop response group. The combined response is sent to all of the bus accessible memory devices on the cache bus line.
摘要翻译：一种用于处理和处理处理器请求的多处理器系统总线协议系统和方法，所述多处理器系统具有被窥探的多个总线可访问存储器件。至少有一条总线。提供了来自总线可访问存储器设备的不同类型的窥探响应的侦听响应组。在每个窥探响应组中提供不同的传输类型。指定提供总线主机信号的总线主设备。总线主设备接收处理器请求。根据处理器请求适当地指定其中一个侦听响应组和传输类型之一。总线主机信号由侦听响应组，传输类型，有效请求信号和高速缓存线地址来制定。总线主机信号被发送到高速缓存总线上的所有总线可访问存储器件和组合响应逻辑系统。基于指定的窥探响应组，高速缓存总线上的所有总线可访问存储器件响应于总线主机信号发送窥探响应。侦听响应被发送到组合的响应逻辑系统。基于由指定和锁存的窥探响应组确定的适当的组合响应编码逻辑来确定组合响应逻辑系统的组合响应。组合的响应被发送到高速缓存总线上的所有总线可访问存储器件。

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