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31. 发明授权

US06397298B1 Cache memory having a programmable cache replacement scheme 失效
标题翻译：具有可编程高速缓存替换方案的高速缓冲存储器
公开(公告)号：US06397298B1
公开(公告)日：2002-05-28
申请号：US09364573
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/121 , G06F12/123
摘要： A cache memory having a programmable cache replacement scheme is disclosed. After a cache “miss,” a linefill operation is first preformed on a cache line. Subsequent to the linefill operation, the cache line is then assigned to an access status other than the most recently used status. The assignment of the access status is based on a programmable setting that defines an access status after a linefill operation and all other subsequent accesses.
摘要翻译：公开了具有可编程高速缓存替换方案的高速缓冲存储器。在缓存“未命中”之后，首先在高速缓存行上执行一个线路填充操作。在行填充操作之后，然后将高速缓存行分配给不同于最近使用状态的访问状态。访问状态的分配基于可编程设置，该设置在线路填充操作和所有其他后续访问之间定义访问状态。

32. 发明授权

US06385702B1 High performance multiprocessor system with exclusive-deallocate cache state 失效
标题翻译：具有独占解除缓存状态的高性能多处理器系统
公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译：高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值的计算机系统。如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

33. 发明授权

US06343344B1 System bus directory snooping mechanism for read/castout (RCO) address transaction 失效
标题翻译：系统总线事务与缓存标签的受害者地址
公开(公告)号：US06343344B1
公开(公告)日：2002-01-29
申请号：US09368221
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0859
摘要： In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.
摘要翻译：响应于接收到用于相关数据访问和丢弃操作的组合地址，包括标识包含数据访问目标和丢弃的受害者的同余类的索引，使用索引来定位单个目录访问一致类。然后将同余类中的地址标签与用于数据访问操作的地址标签和用于外推操作的地址标签同时进行比较，并酌情生成单独的命中信号。然而，仅需要单个目录访问，而不是如已知技术中所需的两个单独的目录访问，利用数据访问目标和丢弃的受害者都属于单个同余类的事实。响应延迟也得到改善，地址总线带宽利用率也得到提高。

34. 发明授权

US06324617B1 Method and system for communicating tags of data access target and castout victim in a single data transfer 失效
标题翻译：用于在单个数据传输中传送数据访问目标和丢弃受害者的标签的方法和系统
公开(公告)号：US06324617B1
公开(公告)日：2001-11-27
申请号：US09368222
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0859
摘要： A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
摘要翻译：组合的地址总线事务包含用于数据访问操作目标的地址标签，要替换的受害者的地址标签，以及标识包括目标和受害者的一致类的地址索引字段。目的地状态信息，例如用于投放受害者的一致性状态和/或LRU位置也可以附加到总线操作中的索引字段和目标和受害者地址标签。从而改善了地址总线带宽利用率，消除了根据现有实践分离数据访问和丢弃操作所采用的索引字段的重复传输。可以同时确定受害者是否可以在形成组合地址的存储设备内找到目标，从而提高该设备的整体性能。

35. 发明授权

US06970976B1 Layered local cache with lower level cache optimizing allocation mechanism 有权
标题翻译：分层本地缓存，具有较低级别的缓存优化分配机制
公开(公告)号：US06970976B1
公开(公告)日：2005-11-29
申请号：US09340074
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F12/08 , G06F12/10 , G06F12/14
CPC分类号： G06F12/0897 , G06F12/0831 , G06F12/0859 , G06F12/1027
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (Li) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上层（Li）高速缓存（上级缓存也可能不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

36. 发明授权

US06629209B1 Cache coherency protocol permitting sharing of a locked data granule 失效
标题翻译：缓存一致性协议允许共享锁定的数据粒子
公开(公告)号：US06629209B1
公开(公告)日：2003-09-30
申请号：US09437185
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. The additional cache states allow cache state transition sequences to be optimized by replacing frequently-occurring and inefficient MESI code sequences with improved sequences using modified cache states.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。额外的高速缓存状态允许通过使用修改的高速缓存状态替换具有改进的序列的频繁出现的和低效的MESI码序列来优化高速缓存状态转换序列。

37. 发明授权

US06625701B1 Extended cache coherency protocol with a modified store instruction lock release indicator 失效
标题翻译：扩展缓存一致性协议，具有修改后的存储指令锁定释放指示器
公开(公告)号：US06625701B1
公开(公告)日：2003-09-23
申请号：US09437183
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1214
CPC分类号： G06F12/0811 , G06F12/0815
摘要： A multiprocessor data processing system requires careful management to maintain cache coherency. Conventional systems using a MESI approach sacrifice some performance with inefficient lock-acquisition and lock-retention techniques. The disclosed system provides additional cache states, indicator bits, and lock-acquisition routines to improve cache performance. In particular, as multiple processors compete for the same cache line, a significant amount of processor time is lost determining if another processor's cache line lock has been released and attempting to reserve that cache line while it is still owned by the other processor. The preferred embodiment provides an indicator bit with the cache store command which specifically indicates whether the store also acts as a lock-release.
摘要翻译：多处理器数据处理系统需要仔细管理以保持高速缓存一致性。使用MESI方法的常规系统通过低效的锁定采集和锁定保留技术来牺牲一些性能。所公开的系统提供附加的高速缓存状态，指示符位和锁定采集例程以提高高速缓存性能。特别地，由于多个处理器竞争相同的高速缓存行，所以丢失了大量的处理器时间，这确定了另一个处理器的高速缓存行锁定是否已被释放，并尝试在该另一个处理器仍然拥有的情况下保留该高速缓存行。优选实施例提供具有高速缓存存储命令的指示符位，其特别地指示存储还是否用作锁定释放。

38. 发明授权

US06571322B2 Multiprocessor computer system with sectored cache line mechanism for cache intervention 有权
标题翻译：多处理器计算机系统，具有缓存线缓存干预机制
公开(公告)号：US06571322B2
公开(公告)日：2003-05-27
申请号：US09752863
申请日：2000-12-28
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0831
摘要： A method of maintaining coherency in a multiprocessor computer system wherein each processing unit's cache has sectored cache lines. A first cache coherency state is assigned to one of the sectors of a particular cache line, and a second cache coherency state, different from the first cache coherency state, is assigned to the overall cache line while maintaining the first cache coherency state for the first sector. The first cache coherency state may provide an indication that the first sector contains a valid value which is not shared with any other cache (i.e., an exclusive or modified state), and the second cache coherency state may provide an indication that at least one of the sectors in the cache line contains a valid value which is shared with at least one other cache (a shared, recently-read, or tagged state). Other coherency states may be applied to other sectors in the same cache line. Partial intervention may be achieved by issuing a request to retrieve an entire cache line, and sourcing only a first sector of the cache line in response to the request. A second sector of the same cache line may be sourced from a third cache. Other sectors may also be sourced from a system memory device of the computer system as well. Appropriate system bus codes-are utilized to transmit cache operations to the system bus and indicate which sectors of the cache line are targets of the cache operation.
摘要翻译：一种在多处理器计算机系统中维持一致性的方法，其中每个处理单元的高速缓冲存储器具有高速缓存行。第一高速缓存一致性状态被分配给特定高速缓存行的一个扇区，并且与第一高速缓存一致性状态不同的第二高速缓存一致性状态被分配给总高速缓存行，同时保持第一高速缓存一致性状态部门。第一高速缓存一致性状态可以提供第一扇区包含不与任何其它高速缓存共享的有效值（即，排他或修改状态）的指示，并且第二高速缓存一致性状态可以提供以下指示：高速缓存行中的扇区包含与至少一个其他高速缓存（共享，最近读取或标记状态）共享的有效值。其他一致性状态可以应用于同一高速缓存行中的其他扇区。部分干预可以通过发出检索整个高速缓存线的请求来实现，并且仅响应于该请求仅提供高速缓存行的第一扇区。相同高速缓存行的第二扇区可以来自第三高速缓存。其他扇区也可以来自计算机系统的系统存储器设备。使用适当的系统总线代码来将高速缓存操作发送到系统总线，并指示高速缓存行的哪些扇区是高速缓存操作的目标。

39. 发明授权

US06470427B1 Programmable agent and method for managing prefetch queues 有权
标题翻译：用于管理预取队列的可编程代理和方法
公开(公告)号：US06470427B1
公开(公告)日：2002-10-22
申请号：US09436373
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , James Stephen Fields, Jr. , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A programmable agent and method for managing prefetch queues provide dynamically configurable handling of priorities in a prefetching subsystem for providing look-ahead memory loads in a computer system. When it's queues are at capacity an agent handling prefetches from memory either ignores new requests, forces the new requests to retry or cancels a pending request in order to perform the new request. The behavior can be adjusted under program control by programming a register, or the control may be coupled to a load pattern analyzer. In addition, the behavior with respect to new requests can be set to different types depending on a phase of a pending request.
摘要翻译：用于管理预取队列的可编程代理和方法为预取子系统中的优先级提供动态可配置的处理，以在计算机系统中提供先行存储器负载。当队列处理能力时，代理处理来自内存的预取将忽略新的请求，强制新的请求重试或取消挂起的请求，以执行新的请求。通过对寄存器进行编程，可以在程序控制下调整行为，或者控制可以耦合到负载模式分析器。此外，根据待处理请求的阶段，关于新请求的行为可以被设置为不同的类型。

40. 发明授权

US06360299B1 Extended cache state with prefetched stream ID information 失效
标题翻译：扩展缓存状态与预取流ID信息
公开(公告)号：US06360299B1
公开(公告)日：2002-03-19
申请号：US09345644
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie , James Stephen Fields, Jr.
IPC分类号： G06F1200
CPC分类号： G06F12/0862 , G06F12/121 , G06F2212/6028
摘要： A method of operating a computer system is disclosed in which an instruction having an explicit prefetch request is issued directly from an instruction sequence unit to a prefetch unit of a processing unit. In a preferred embodiment, two prefetch units are used, the first prefetch unit being hardware independent and dynamically monitoring one or more active streams associated with operations carried out by a core of the processing unit, and the second prefetch unit being aware of the lower level storage subsystem and sending with the prefetch request an indication that a prefetch value is to be loaded into a lower level cache of the processing unit. The invention may advantageously associate each prefetch request with a stream ID of an associated processor stream, or a processor ID of the requesting processing unit (the latter feature is particularly useful for caches which are shared by a processing unit cluster). If another prefetch value is requested from the memory hierarchy, and it is determined that a prefetch limit of cache usage has been met by the cache, then a cache line in the cache containing one of the earlier prefetch values is allocated for receiving the other prefetch value.
摘要翻译：公开了一种操作计算机系统的方法，其中具有显式预取请求的指令直接从指令序列单元发送到处理单元的预取单元。在优选实施例中，使用两个预取单元，第一预取单元是硬件独立的，并且动态地监视与由处理单元的核心执行的操作相关联的一个或多个活动流，并且第二预取单元知道较低级别存储子系统，并用预取请求发送将预取值加载到处理单元的较低级缓存中的指示。本发明可以有利地将每个预取请求与相关联的处理器流的流ID或请求处理单元的处理器ID相关联（后一特征对于由处理单元簇共享的高速缓存特别有用）。如果从存储器层次结构请求另一个预取值，并且确定高速缓存的高速缓存使用的预取限制已经被高速缓存满足，则分配包含较早预取值之一的高速缓存行中的高速缓存行用于接收另一个预取值。

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