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31. 发明授权

US06615320B2 Store collapsing mechanism for SMP computer system 有权
公开(公告)号：US06615320B2
公开(公告)日：2003-09-02
申请号：US09782580
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0815 , G06F12/0831
摘要： A method of handling a write operation in a multiprocessor computer system wherein each processing unit has a respective cache, by determining that a new value for a store instruction is the same as a current value already contained in the memory hierarchy, and discarding the store instruction without issuing any associated cache operation in response to this determination. When a store hit occurs, the current value is retrieved from the local cache. When a store miss occurs, the current value is retrieved from a remote cache by issuing a read request. The comparison may be performed using a portion of the cache line which is less than a granule size of the cache line. A store gathering queue can be use to collect pending store instructions that are directed to different portions of the same cache line.

32. 发明授权

US06574714B2 Efficient instruction cache coherency maintenance mechanism for scalable multiprocessor computer system with write-back data cache 有权
公开(公告)号：US06574714B2
公开(公告)日：2003-06-03
申请号：US09782579
申请日：2001-02-12
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/0811 , G06F12/0831 , G06F12/0848
摘要： A method of maintaining coherency in a cache hierarchy of a processing unit of a computer system, wherein the upper level (L1) cache includes a split instruction/data cache. In one implementation, the L1 data cache is store-through, and each processing unit has a lower level (L2) cache. When the lower level cache receives a cache operation requiring invalidation of a program instruction in the L1 instruction cache (i.e., a store operation or a snooped kill), the L2 cache sends an invalidation transaction (e.g., icbi) to the instruction cache. The L2 cache is fully inclusive of both instructions and data. In another implementation, the L1 data cache is write-back, and a store address queue in the processor core is used to continually propagate pipelined address sequences to the lower levels of the memory hierarchy, i.e., to an L2 cache or, if there is no L2 cache, then to the system bus. If there is no L2 cache, then the cache operations may be snooped directly against the L1 instruction cache.

33. 发明授权

US06477613B1 Cache index based system address bus 有权
标题翻译：基于缓存索引的系统地址总线
公开(公告)号：US06477613B1
公开(公告)日：2002-11-05
申请号：US09345302
申请日：1999-06-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0895 , G06F12/0897
摘要： Following a cache miss by an operation, the address for the operation is transmitted on the bus coupling the cache to lower levels of the storage hierarchy. A portion of the address including the index field is transmitted during a first bus cycle, and may be employed to begin directory lookups in lower level storage devices before the address tag is received. The remainder of the address is transmitted during subsequent bus cycles, which should be in time for address tag comparisons with the congruence class elements. To allow multiple directory lookups to be occurring concurrently in a pipelined directory, a portion of multiple addresses for several data access operations, each portion including the index field for the respective address, may be transmitted during the first bus cycle or staged in consecutive bus cycles, with the remainders of each address—including the cache tags—transmitted during the subsequent bus cycles. This allows directory lookups utilizing the index fields to be processed concurrently within a lower level storage device for multiple operations, with the address tags being provided later, but still timely for tag comparisons at the end of the directory lookup. Where the lower level storage device operates at a higher frequency than the bus, overall latency is reduced and directory bandwidth is more efficiently utilized.
摘要翻译：在操作的高速缓存未命中之后，操作的地址在将高速缓存耦合到存储层级的较低级别的总线上传输。包括索引字段的地址的一部分在第一总线周期期间被发送，并且可以用于在接收到地址标签之前开始下级存储设备中的目录查找。在随后的总线周期期间传送地址的其余部分，这些时间应与地址标签与同余类元素进行比较。为了允许在流水线目录中同时发生多个目录查找，可以在第一个总线周期期间发送多个数据访问操作的多个地址的一部分，每个部分包括相应地址的索引字段，或者在连续的总线周期中分段，每个地址的剩余部分，包括在后续总线周期期间发送的缓存标签。这允许使用索引字段的目录查找在较低级存储设备中同时处理以用于多个操作，其中地址标签稍后提供，但是在目录查找结束时仍然适合于标签比较。在较低级存储设备以比总线更高的频率工作的地方，总体延迟降低，目录带宽更有效地利用。

34. 发明授权

US06434670B1 Method and apparatus for efficiently managing caches with non-power-of-two congruence classes 失效
标题翻译：有效管理具有非二次全能级别的缓存的方法和装置
公开(公告)号：US06434670B1
公开(公告)日：2002-08-13
申请号：US09435948
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0864 , G06F12/123
摘要： A method and apparatus for efficiently managing caches with non-power-of-two congruence classes allows for increasing the number of congruence classes in a cache when not enough area is available to double the cache size. One or more congruence classes within the cache have their associative sets split so that a number of congruence classes are created with reduced associativity. The management method and apparatus allow access to the congruence classes without introducing any additional cycles of delay or complex logic.
摘要翻译：一种用于非有效二等度类的高效管理高速缓存的方法和装置允许当没有足够的区域可用于使高速缓存大小加倍时，增加高速缓存中的同余类的数量。高速缓存中的一个或多个同余类别将其关联集合拆分，从而创建具有降低的关联性的多个同余类。管理方法和装置允许访问一致类，而不引入任何额外的延迟周期或复杂的逻辑。

35. 发明授权

US06434667B1 Layered local cache with imprecise reload mechanism 有权
标题翻译：分层本地缓存与不精确的重载机制
公开(公告)号：US06434667B1
公开(公告)日：2002-08-13
申请号：US09340075
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0811 , G06F12/0859 , G06F12/0888
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

36. 发明授权

US06418513B1 Queue-less and state-less layered local data cache mechanism 失效
标题翻译：无队列和无状态的分层本地数据缓存机制
公开(公告)号：US06418513B1
公开(公告)日：2002-07-09
申请号：US09340077
申请日：1999-06-25
申请人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , Leo James Clark , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1200
CPC分类号： G06F12/0897
摘要： A method of improving memory access for a computer system, by sending load requests to a lower level storage subsystem along with associated information pertaining to intended use of the requested information by the requesting processor, without using a high level load queue. Returning the requested information to the processor along with the associated use information allows the information to be placed immediately without using reload buffers. A register load bus separate from the cache load bus (and having a smaller granularity) is used to return the information. An upper level (L1) cache may then be imprecisely reloaded (the upper level cache can also be imprecisely reloaded with store instructions). The lower level (L2) cache can monitor L1 and L2 cache activity, which can be used to select a victim cache block in the L1 cache (based on the additional L2 information), or to select a victim cache block in the L2 cache (based on the additional L1 information). L2 control of the L1 directory also allows certain snoop requests to be resolved without waiting for L1 acknowledgement. The invention can be applied to, e.g., instruction, operand data and translation caches.
摘要翻译：一种改进计算机系统的存储器访问的方法，通过将请求发送到较低级别的存储子系统以及由请求处理器对与请求的信息的预期用途有关的关联信息而不使用高级别的负载队列来进行发送。将所请求的信息与相关联的使用信息一起返回到处理器允许立即放置信息而不使用重新加载缓冲器。使用与缓存负载总线分离（并具有较小粒度）的寄存器负载总线返回信息。然后可能不精确地重新加载上级（L1）高速缓存（高级缓存也可以不精确地用存储指令重新加载）。低级（L2）缓存可以监视L1和L2高速缓存活动，其可用于在L1高速缓存中选择受害者缓存块（基于附加的L2信息），或者选择L2缓存中的受害缓存块（基于附加的L1信息）。 L1目录的L2控制也允许解决某些侦听请求，而无需等待L1确认。本发明可以应用于例如指令，操作数数据和翻译高速缓存。

37. 发明授权

US06397298B1 Cache memory having a programmable cache replacement scheme 失效
标题翻译：具有可编程高速缓存替换方案的高速缓冲存储器
公开(公告)号：US06397298B1
公开(公告)日：2002-05-28
申请号：US09364573
申请日：1999-07-30
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie
IPC分类号： G06F1208
CPC分类号： G06F12/121 , G06F12/123
摘要： A cache memory having a programmable cache replacement scheme is disclosed. After a cache “miss,” a linefill operation is first preformed on a cache line. Subsequent to the linefill operation, the cache line is then assigned to an access status other than the most recently used status. The assignment of the access status is based on a programmable setting that defines an access status after a linefill operation and all other subsequent accesses.
摘要翻译：公开了具有可编程高速缓存替换方案的高速缓冲存储器。在缓存“未命中”之后，首先在高速缓存行上执行一个线路填充操作。在行填充操作之后，然后将高速缓存行分配给不同于最近使用状态的访问状态。访问状态的分配基于可编程设置，该设置在线路填充操作和所有其他后续访问之间定义访问状态。

38. 发明授权

US06385702B1 High performance multiprocessor system with exclusive-deallocate cache state 失效
标题翻译：具有独占解除缓存状态的高性能多处理器系统
公开(公告)号：US06385702B1
公开(公告)日：2002-05-07
申请号：US09437198
申请日：1999-11-09
申请人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
发明人： Ravi Kumar Arimilli , Lakshminarayana Baba Arimilli , John Steven Dodson , Guy Lynn Guthrie , William John Starke
IPC分类号： G06F1200
CPC分类号： G06F12/0831 , G06F12/0811
摘要： A cache coherency protocol uses a “Exclusive-Deallocate” (ED) coherency state to indicate that a particular value is currently held in an upper level cache in an exclusive, unmodified form (not shared with any other caches of the computer system, including caches associated with the same processing unit), so that the value can conveniently be modified without any lower level bus transactions since no lower level caches have allocated a line for the value. If the value is subsequently modified in the upper level cache, its coherency state is simply switched to “modified” without the need for any bus transactions. Conversely, if the value is evicted from the upper level cache without ever having been modified, it can be loaded into the lower level cache with a coherency state indicating that the lower level cache contains the unmodified value exclusive of all other caches in other processing units of the computer system. If the value is initially loaded into the upper level cache from a cache of another processing unit, or from a lower level cache of the same processing unit, then the upper level cache may be selectively programmed to mark the cache line with the ED state.
摘要翻译：高速缓存一致性协议使用“独占解除分配”（ED）一致性状态来指示特定值当前以独占未修改的形式（不与计算机系统的任何其他高速缓存共享，包括高速缓存）保持在高级缓存中与相同的处理单元关联），使得该值可以方便地被修改而没有任何较低级别的总线事务，因为没有较低级别的高速缓存已经为该值分配了一行。如果该值随后在高级缓存中被修改，则其一致性状态被简单地切换到“修改”，而不需要任何总线事务。相反，如果该值从上级缓存中被逐出而没有被修改，则可以将其加载到具有一致性状态的相关性状态中，该相关性状态指示低级缓存包含其他处理单元中所有其他高速缓存的排他性的未修改值的计算机系统。如果该值最初从另一处理单元的高速缓存或相同处理单元的较低级高速缓存加载到高级缓存中，则可以选择性地编程高级缓存以用ED状态标记高速缓存行。

39. 发明授权

US06343344B1 System bus directory snooping mechanism for read/castout (RCO) address transaction 失效
标题翻译：系统总线事务与缓存标签的受害者地址
公开(公告)号：US06343344B1
公开(公告)日：2002-01-29
申请号：US09368221
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1208
CPC分类号： G06F12/0804 , G06F12/0859
摘要： In response to receiving a combined address for related data access and cast out operations, including an index identifying a congruence class containing both the target of the data access and the victim of the cast out, a single directory access is performed utilizing the index to locate the congruence class. Address tags within the congruence class are then compared to the address tag for the data access operation and the address tag for the cast out operation concurrently, generating separate hit signals as appropriate. Only a single directory access is required, however, rather than two separate directory accesses as required in the known art, taking advantage of the fact that both the data access target and the cast out victim belong to a single congruence class. Response latency is also improved, as is address bus bandwidth utilization.
摘要翻译：响应于接收到用于相关数据访问和丢弃操作的组合地址，包括标识包含数据访问目标和丢弃的受害者的同余类的索引，使用索引来定位单个目录访问一致类。然后将同余类中的地址标签与用于数据访问操作的地址标签和用于外推操作的地址标签同时进行比较，并酌情生成单独的命中信号。然而，仅需要单个目录访问，而不是如已知技术中所需的两个单独的目录访问，利用数据访问目标和丢弃的受害者都属于单个同余类的事实。响应延迟也得到改善，地址总线带宽利用率也得到提高。

40. 发明授权

US06324617B1 Method and system for communicating tags of data access target and castout victim in a single data transfer 失效
标题翻译：用于在单个数据传输中传送数据访问目标和丢弃受害者的标签的方法和系统
公开(公告)号：US06324617B1
公开(公告)日：2001-11-27
申请号：US09368222
申请日：1999-08-04
申请人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
发明人： Ravi Kumar Arimilli , John Steven Dodson , Guy Lynn Guthrie , Jody B. Joyner , Jerry Don Lewis
IPC分类号： G06F1200
CPC分类号： G06F12/0804 , G06F12/0859
摘要： A combined address bus transaction contains the address tag for a data access operation target, the address tag for a victim to be replaced, and the address index field identifying the congruence class including both the target and the victim. Directory state information such as coherency state and/or LRU position for the cast out victim may also be appended to the index field and target and victim address tags within the bus operation. Address bus bandwidth utilization is thereby improved, eliminating duplicate transmission of the index field employed by separate data access and cast out operations in accordance with the existing practice. The victim may be prospectively selected concurrently with the determination of whether the target may be found within the storage device forming the combined address, improving overall performance for that device.
摘要翻译：组合的地址总线事务包含用于数据访问操作目标的地址标签，要替换的受害者的地址标签，以及标识包括目标和受害者的一致类的地址索引字段。目的地状态信息，例如用于投放受害者的一致性状态和/或LRU位置也可以附加到总线操作中的索引字段和目标和受害者地址标签。从而改善了地址总线带宽利用率，消除了根据现有实践分离数据访问和丢弃操作所采用的索引字段的重复传输。可以同时确定受害者是否可以在形成组合地址的存储设备内找到目标，从而提高该设备的整体性能。

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