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31. 发明授权

US5598537A Apparatus and method for driving a bus to a docking safe state in a dockable computer system including a docking station and a portable computer 失效
标题翻译：一种用于在包括对接站和便携式计算机的可对接计算机系统中将总线驱动到对接安全状态的装置和方法
公开(公告)号：US5598537A
公开(公告)日：1997-01-28
申请号：US280314
申请日：1994-07-26
申请人： Scott Swanstrom , Douglas D. Gephardt
发明人： Scott Swanstrom , Douglas D. Gephardt
IPC分类号： G06F1/18 , G06F1/16 , G06F3/00 , G06F13/364 , G06F13/40 , H05K7/10 , G06F13/00
CPC分类号： G06F1/1632 , G06F13/364 , G06F13/4036 , G06F13/4072 , G06F13/4081
摘要： In a dockable computer system capable of hot docking or warm docking, a docking safe circuit drives the bus of the portable computer and docking station to a docking safe state in response to a DOCK signal. The DOCK signal may be a notice signal indicative of a change of state from the undocked state to the docked state or from the docked state to the undocked state. The notice signal may be provided from software, a user-actuated switch or an infrared signal. Preferably, the docking safe state or dockable state is a state in which: the ground conductors of the buses are referenced to a common ground potential; the buses are "quiet" or non-transitioning; the bidirectional terminals on the bus of the portable computer are set to an output state; the bidirectional terminals of the bus of the docking station are set to an input state; and the signaling levels of the buses have the same voltage potential. Preferably, the present invention is implemented on a peripheral component interconnect (PCI) bus.
摘要翻译：在能够热对接或热对接的可停靠的计算机系统中，对接安全电路响应于DOCK信号将便携式计算机和坞站的总线驱动到对接安全状态。 DOCK信号可以是指示状态从脱离状态到对接状态或从停靠状态到解除停止状态的通知信号。通知信号可以由软件，用户致动的开关或红外信号提供。优选地，对接安全状态或可停靠状态是这样的状态，其中：总线的接地导体参考公共地电位; 公共汽车是“安静的”还是非转型的; 便携式计算机总线上的双向终端设置为输出状态; 对接站的总线的双向端子被设置为输入状态; 并且总线的信号电平具有相同的电压电位。优选地，本发明在外围组件互连（PCI）总线上实现。

32. 发明授权

US5060138A Apparatus for use with a computing device for generating a substitute acknowledgement to an input when the computing device is in an operational hiatus 失效
标题翻译：用于与计算设备一起使用的装置，用于在计算设备处于操作中断时向输入生成替代确认
公开(公告)号：US5060138A
公开(公告)日：1991-10-22
申请号：US576695
申请日：1990-08-31
申请人： Douglas D. Gephardt , Peggy Avalos
发明人： Douglas D. Gephardt , Peggy Avalos
IPC分类号： G06F1/04 , G06F13/36 , G11C11/406
CPC分类号： G06F13/36 , Y02B60/1228
摘要： The invention is an apparatus for use with a computing device for generating a substitute acknowledgement to a first input signal when the computing device is in an operational hiatus. The apparatus comprises a logical processing circuit for indicating presence of the first input signal depending upon the state of a second input signal, and a logical circuit for producing an output signal which is representative of a selection of one of the plurality of logical inputs. The selection of logical inputs is determined by the state of the second input signal. The first input signal is a hold request signal and comprises a first logical input to the logical processing circuit. A second logical input is a hold acknowledgement signal which is generated by the computing device in response to the presence of the first input signal when the computing device is not in an operational hiatus.

33. 发明授权

US08249730B2 Systems and methods for shadowing an HDA codec 失效
标题翻译：用于屏蔽HDA编解码器的系统和方法
公开(公告)号：US08249730B2
公开(公告)日：2012-08-21
申请号：US12202360
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F17/00
CPC分类号： G06F3/162
摘要： Systems and methods for “shadowing” a target codec to provide additional features that are not available in the target codec. In one embodiment, an audio amplification system includes a High Definition Audio (HDA) bus, and an HDA controller, a conventional HDA codec and a shadow HDA codec coupled to the HDA bus. The conventional codec receives audio data and commands from the HDA controller via the bus and processes them to generate an output audio signal. The shadow codec snoops the audio data and commands on the HDA bus that are targeted to the conventional codec. The shadow codec processes the snooped audio data and commands to generate a second audio output. The shadow codec does not communicate with the HDA controller and is transparent to the controller. The shadow codec does not request enumeration from the HDA controller and does not receive an address from the HDA controller.
摘要翻译：用于“遮蔽”目标编解码器以提供目标编解码器中不可用的附加功能的系统和方法。在一个实施例中，音频放大系统包括高清晰度音频（HDA）总线和HDA控制器，传统的HDA编解码器和耦合到HDA总线的影子HDA编解码器。常规编解码器经由总线从HDA控制器接收音频数据和命令，并处理它们以产生输出音频信号。影子编解码器侦听HDA总线上的传统编解码器的音频数据和命令。影子编解码器处理窥探的音频数据和命令以产生第二个音频输出。影子编解码器不与HDA控制器通信，对控制器是透明的。影子编解码器不要求来自HDA控制器的枚举，也不会从HDA控制器接收地址。

34. 发明授权

US08219226B2 Systems and methods for overriding hardwired responses in an HDA codec 失效
标题翻译：用于覆盖HDA编解码器中的硬连线响应的系统和方法
公开(公告)号：US08219226B2
公开(公告)日：2012-07-10
申请号：US12202358
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
IPC分类号： G06F17/00 , G06F13/00 , G06F9/30 , G06F9/40
CPC分类号： G06F3/162
摘要： Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.
摘要翻译：用于将编解码器的硬连线响应覆盖从HDA控制器接收的高清晰度音频（HDA）动词的系统和方法。在一个实施例中，HDA编解码器被配置为存储一个或多个覆盖的响应，每一个响应与相应的HDA动词相关联。当编解码器接收到HDA动词时，编解码器确定动词是否与其中一个重写的响应相关联。如果动词与其中一个覆盖的响应相关联，则覆盖的响应将返回给HDA控制器。如果第一HDA动词与存储的覆盖应答之一不相关联，则向HDA总线提供与第一HDA动词相关联的硬连线响应。可以仅针对不支持的动词或任何提示响应的动词返回重写响应。

35. 发明申请

US20090063828A1 Systems and Methods for Communication between a PC Application and the DSP in a HDA Audio Codec 审中-公开
标题翻译： PC应用程序与HDA音频编解码器中的DSP之间的通信系统和方法
公开(公告)号：US20090063828A1
公开(公告)日：2009-03-05
申请号：US12202356
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F9/315
CPC分类号： G06F3/162
摘要： Systems and methods implemented in a PC for enabling communication between an application executing on the CPU and a DSP that is incorporated into a codec in the High Definition Audio (HDA) system, wherein the communication is carried out via the HDA bus. In one embodiment, an HDA codec includes one or more conventional HDA widgets coupled to a programmable processor such as a DSP. The codec includes a set of registers that are configured to store HDA verbs and data transmitted via the HDA bus. The programmable processor is configured to identify verbs that indicate associated information is a communication from an application executing on the CPU, read the associated information, and process the information according to the associated verbs. The information may be program instructions, parametric data, requests for information, etc.
摘要翻译：在PC中实现的用于实现在CPU上执行的应用程序与被并入高清晰度音频（HDA）系统中的编解码器的DSP之间的通信的系统和方法，其中通过HDA总线进行通信。在一个实施例中，HDA编解码器包括耦合到诸如DSP的可编程处理器的一个或多个常规HDA小部件。编解码器包括一组寄存器，用于存储通过HDA总线传输的HDA动词和数据。可编程处理器被配置为识别指示相关信息的动词是来自在CPU上执行的应用程序的通信，读取相关联的信息，以及根据相关联的动词处理信息。该信息可以是程序指令，参数数据，信息请求等。

36. 发明申请

US20090063738A1 Systems and Methods for Overriding Hardwired Responses in an HDA Codec 失效
标题翻译：用于覆盖HDA编解码器中的硬连线响应的系统和方法
公开(公告)号：US20090063738A1
公开(公告)日：2009-03-05
申请号：US12202358
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas
IPC分类号： G06F13/42
CPC分类号： G06F3/162
摘要： Systems and methods for overriding hardwired responses of a codec to High Definition Audio (HDA) verbs that are received from an HDA controller. In one embodiment, an HDA codec is configured to store one or more overriding responses, each of which is associated with a corresponding HDA verb. When an HDA verb is received by the codec, the codec determines whether the verb is associated with one of the overriding responses. If the verb is associated with one of the overriding responses, the overriding response is returned to the HDA controller. If the first HDA verb is not associated with one of the stored overriding responses, provide a hardwired response associated with the first HDA verb to the HDA bus. Overriding responses can be returned for unsupported verbs only, or for any verbs that prompt responses.
摘要翻译：用于将编解码器的硬连线响应覆盖从HDA控制器接收的高清晰度音频（HDA）动词的系统和方法。在一个实施例中，HDA编解码器被配置为存储一个或多个覆盖的响应，每一个响应与相应的HDA动词相关联。当编解码器接收到HDA动词时，编解码器确定动词是否与其中一个重写的响应相关联。如果动词与其中一个覆盖的响应相关联，则覆盖的响应将返回给HDA控制器。如果第一HDA动词与存储的覆盖应答之一不相关联，则向HDA总线提供与第一HDA动词相关联的硬连线响应。可以仅针对不支持的动词或任何提示响应的动词返回重写响应。

37. 发明申请

US20090062948A1 Systems and Methods for Controlling Audio Volume in the Processor of a High Definition Audio Codec 失效
标题翻译：用于控制高分辨率音频编解码器处理器中音频音量的系统和方法
公开(公告)号：US20090062948A1
公开(公告)日：2009-03-05
申请号：US12202355
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Larry E. Hand , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： G06F17/00
CPC分类号： H03G3/3089 , G06F3/16 , G10L15/26 , G11B20/10527 , G11B2020/10574 , H03F3/217
摘要： Systems and methods for controlling the audio volume of an audio signal in an HDA codec having a programmable processor such as a DSP, wherein the codec receives digital audio signals and audio volume control verbs over an HDA bus, and the audio volume levels associated with the audio volume control verbs are used by the processor in the generation pulse width modulated (PWM) output signals, thereby controlling the audio volume levels of the output signals. The processor may be configured to adjust non-volume parameters such as PWM deadtime, in addition to adjusting audio volume, based on the audio volume levels. The codec may be implemented in a PC or other system that implements an HDA system that includes the HDA bus and HDA codec.
摘要翻译：用于控制具有诸如DSP的可编程处理器的HDA编解码器中的音频信号的音频音量的系统和方法，其中编解码器通过HDA总线接收数字音频信号和音频音量控制动词，以及与音频音量控制动词由处理器在生成脉宽调制（PWM）输出信号中使用，从而控制输出信号的音频音量。除了根据音频音量水平调整音频音量之外，处理器可以被配置为调整诸如PWM死时间之类的非体积参数。编解码器可以在实现包括HDA总线和HDA编解码器的HDA系统的PC或其他系统中实现。

38. 发明申请

US20090060228A1 Systems and Methods for Shadowing an HDA Codec 失效
标题翻译：用于影像HDA编解码器的系统和方法
公开(公告)号：US20090060228A1
公开(公告)日：2009-03-05
申请号：US12202360
申请日：2008-09-01
申请人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
发明人： Daniel L. Chieng , Douglas D. Gephardt , Jeffrey M. Klaas , Adam Zaharias
IPC分类号： H03F21/00 , G06F3/00
CPC分类号： G06F3/162
摘要： Systems and methods for “shadowing” a target codec to provide additional features that are not available in the target codec. In one embodiment, an audio amplification system includes a High Definition Audio (HDA) bus, and an HDA controller, a conventional HDA codec and a shadow HDA codec coupled to the HDA bus. The conventional codec receives audio data and commands from the HDA controller via the bus and processes them to generate an output audio signal. The shadow codec snoops the audio data and commands on the HDA bus that are targeted to the conventional codec. The shadow codec processes the snooped audio data and commands to generate a second audio output. The shadow codec does not communicate with the HDA controller and is transparent to the controller. The shadow codec does not request enumeration from the HDA controller and does not receive an address from the HDA controller.
摘要翻译：用于“遮蔽”目标编解码器以提供目标编解码器中不可用的附加功能的系统和方法。在一个实施例中，音频放大系统包括高清晰度音频（HDA）总线和HDA控制器，传统的HDA编解码器和耦合到HDA总线的影子HDA编解码器。常规编解码器经由总线从HDA控制器接收音频数据和命令，并处理它们以产生输出音频信号。影子编解码器侦听HDA总线上的传统编解码器的音频数据和命令。影子编解码器处理窥探的音频数据和命令以产生第二个音频输出。影子编解码器不与HDA控制器通信，对控制器是透明的。影子编解码器不要求来自HDA控制器的枚举，也不会从HDA控制器接收地址。

39. 发明授权

US06499086B2 Processor with decompressed video bus 有权
标题翻译：具有解压缩视频总线的处理器
公开(公告)号：US06499086B2
公开(公告)日：2002-12-24
申请号：US09770461
申请日：2001-01-29
申请人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
发明人： Steven L. Belt , Douglas D. Gephardt , Drew J. Dutton , Brett B. Stewart , Rita M. Wisor
IPC分类号： G06F1200
CPC分类号： G06F12/0875
摘要： A dedicated bus between a central processing unit and a peripheral unit, such as a graphics controller driving a video display, provides enhanced capability in an environment in which signal processing occurs within the central processing unit. The dedicated bus relieves other data buses, such as the PCI bus, of the need to communicate large amounts of data, such as decompressed video data. The resulting system supports high bandwidth transmissions of decompressed video data, enabling high resolution 24 bit full motion video and multiple data stream video.
摘要翻译：在中央处理单元和周边单元之间的专用总线，例如驱动视频显示器的图形控制器，在中央处理单元内发生信号处理的环境中提供增强的能力。专用总线减轻了诸如PCI总线的其他数据总线，需要传送大量数据，例如解压缩的视频数据。所得到的系统支持解压缩视频数据的高带宽传输，实现高分辨率24位全动态视频和多数据流视频。

40. 发明授权

US5901332A System for dynamically reconfiguring subbusses of data bus according to system needs based on monitoring each of the information channels that make up data bus 失效
标题翻译：根据系统需要动态重新配置数据总线子系统的系统，基于监控构成数据总线的每个信息通道
公开(公告)号：US5901332A
公开(公告)日：1999-05-04
申请号：US921078
申请日：1997-08-29
申请人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Steven L. Belt , Drew J. Dutton
发明人： Douglas D. Gephardt , Brett B. Stewart , Rita M. Wisor , Steven L. Belt , Drew J. Dutton
IPC分类号： G06F13/38 , G06F13/40
CPC分类号： G06F13/4018 , G06F13/385
摘要： A data bus for connecting information processing devices is configurable into a plurality of subbusses in order to fully utilize the data bus capacity. The size and data transfer direction of each subbus, as well as the data transfer speed of each subbus, is independent of the other subbusses. Also, the data bus can be reconfigured to meet changing system requirements. A data bus controller is thus provided to accomplish this data bus reconfiguration. The reconfiguration may be accomplished in accordance with one of a plurality of information flow templates which may be stored in a memory. A method of configuring a data bus is also provided wherein information transfer needs of a system are identified and the data bus is configured according to the identified information transfer means. The reconfiguration in accordance with the information transfer needs may be accomplished in accordance with one or more information flow templates which may be stored in a memory. The system may operate in accordance with a self arbitration scheme such that reconfiguration of the system is based on operational experience, such as utilization rates or excess capacity associated with each of the subbusses.
摘要翻译：用于连接信息处理设备的数据总线可配置成多个子总线，以便充分利用数据总线容量。每个子总线的大小和数据传输方向以及每个子总线的数据传输速度与其他子总线无关。此外，数据总线可以重新配置以满足不断变化的系统要求。因此提供数据总线控制器来完成该数据总线重新配置。重新配置可以根据可存储在存储器中的多个信息流模板之一来完成。还提供了一种配置数据总线的方法，其中识别系统的信息传送需求，并且根据所识别的信息传送装置配置数据总线。根据信息传送需求的重新配置可以根据可存储在存储器中的一个或多个信息流模板来完成。系统可以根据自我仲裁方案操作，使得系统的重新配置基于诸如与每个子总线相关联的利用率或过多容量的操作经验。

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