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31. 发明授权

US07763511B2 Dielectric barrier for nanocrystals 有权
标题翻译：纳米晶体的介电阻挡层
公开(公告)号：US07763511B2
公开(公告)日：2010-07-27
申请号：US11618666
申请日：2006-12-29
申请人： Prashant Majhi , Kyu S. Min , Wilman Tsai
发明人： Prashant Majhi , Kyu S. Min , Wilman Tsai
IPC分类号： H01L21/00
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513
摘要： Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.
摘要翻译：形成这种电子设备和系统的电子设备，系统和方法包括设置在电介质堆叠上的非绝缘纳米晶体，其中非绝缘纳米晶体被布置成存储电荷。电介质堆叠包括具有不同电子势垒的两个电介质层，使得非绝缘纳米晶体可以设置在具有较低电子势垒的电介质层上。

32. 发明申请

US20090294867A1 DUAL METAL GATES USING ONE METAL TO ALTER WORK FUNCTION OF ANOTHER METAL 失效
标题翻译：使用一种金属的双金属门可以改善其他金属的工作功能
公开(公告)号：US20090294867A1
公开(公告)日：2009-12-03
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L29/49 , H01L21/28
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

33. 发明申请

US20090085129A1 DEFECT-FREE SOURCE/DRAIN EXTENSIONS FOR MOSFETS HAVING GERMANIUM BASED CHANNEL REGIONS 有权
标题翻译：具有基于锗的通道区域的MOSFET的无缺陷源/漏极扩展
公开(公告)号：US20090085129A1
公开(公告)日：2009-04-02
申请号：US11864907
申请日：2007-09-29
申请人： Prashant Majhi , William Tsai , Jack Kavalieros
发明人： Prashant Majhi , William Tsai , Jack Kavalieros
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L29/6659 , H01L21/26513 , H01L21/26586 , H01L29/1054 , H01L29/1083 , H01L29/165 , H01L29/7833
摘要： A process for forming defect-free source and drain extensions for a MOSFET built on a germanium based channel region deposits a first silicon germanium layer on a semiconductor substrate, deposits a gate dielectric layer on the silicon germanium layer, and deposits a gate electrode layer on the gate dielectric layer. A dry etch chemistry etches those layers to form a gate electrode, a gate dielectric, and a silicon germanium channel region on the semiconductor substrate. Next, an ion implantation process forms halo implant regions that consume portions of the silicon germanium channel region and the semiconductor substrate. Finally, an in-situ doped epitaxial deposition process grows a pair of silicon germanium layers having LDD regions. The silicon germanium layers are adjacent to the silicon germanium channel region and the halo implant regions do not damage any portion of the silicon germanium layers.
摘要翻译：用于形成用于基于锗基通道区域的MOSFET的无缺陷源极和漏极延伸的工艺在半导体衬底上沉积第一硅锗层，在硅锗层上沉积栅极电介质层，并将栅极电极层沉积在栅介质层。干蚀刻化学蚀刻这些层以在半导体衬底上形成栅电极，栅极电介质和硅锗沟道区。接下来，离子注入工艺形成消耗硅锗沟道区和半导体衬底的部分的卤素注入区。最后，原位掺杂外延沉积工艺生长了一对具有LDD区的硅锗层。硅锗层与硅锗沟道区相邻，并且卤素注入区不会损坏硅锗层的任何部分。

34. 发明申请

US20180004318A1 FLEXIBLE SENSOR 审中-公开
公开(公告)号：US20180004318A1
公开(公告)日：2018-01-04
申请号：US15200949
申请日：2016-07-01
申请人： Khaled Ahmed , Prashant Majhi
发明人： Khaled Ahmed , Prashant Majhi
IPC分类号： G06F3/041 , C23C14/34 , H05K1/09 , C23C16/50 , C23C14/14 , H05K1/02 , H01J37/32 , C23C16/24
CPC分类号： G06F3/041 , G06F2203/04102 , G06F2203/04103 , H01J37/32009 , H01J37/32532 , H01J2237/3321 , H01J2237/334 , H05K1/0271 , H05K1/0346 , H05K1/0393 , H05K1/09 , H05K3/0014 , H05K3/007 , H05K3/027 , H05K3/067 , H05K3/107 , H05K2201/0154 , H05K2201/0323 , H05K2201/0338 , H05K2201/0341 , H05K2201/0385 , H05K2201/0391 , H05K2203/0759 , H05K2203/0769 , H05K2203/107
摘要： Systems, apparatuses, and/or methods to manufacture and/or implement a sensor film, a composite electrode, and/or a computing device such as a flexible device. The sensor film may include a random network of metal lines and graphene interconnecting the metal lines. The composite electrode may be formed from the sensor film. In addition, the composite electrode may include a first portion including a metal layer in a graphene layer, wherein the metal layer is randomly located in the graphene layer, and a second portion excluding the metal layer and including the graphene layer. The sensor film may be patterned to include any composite electrode configuration, such as an antenna electrode configuration, a touch electrode configuration, and so on. Thus, the flexible device may include a flexible touch screen.

35. 发明授权

US09117893B1 Tunneling transistor suitable for low voltage operation 有权
标题翻译：隧道晶体管适用于低电压工作
公开(公告)号：US09117893B1
公开(公告)日：2015-08-25
申请号：US13759478
申请日：2013-02-05
申请人： Chenming Hu , Anupama Bowonder , Pratik Patel , Daniel Chou , Prashant Majhi
发明人： Chenming Hu , Anupama Bowonder , Pratik Patel , Daniel Chou , Prashant Majhi
IPC分类号： H01L29/66 , H01L29/78 , H01L29/08 , H01L29/778 , B82Y99/00
CPC分类号： H01L29/78 , B82Y99/00 , H01L29/0646 , H01L29/0847 , H01L29/0895 , H01L29/165 , H01L29/42312 , H01L29/7391 , H01L29/778 , H01L29/7786
摘要： Several embodiments of a tunneling transistor are disclosed. In one embodiment, a tunneling transistor includes a semiconductor substrate, a source region formed in the semiconductor substrate, a drain region formed in the semiconductor substrate, a gate stack including a metallic gate electrode and a gate dielectric, and a tunneling junction that is substantially parallel to an interface between the metallic gate electrode and the gate dielectric. As a result of the tunneling junction that is substantially parallel with the interface between the metallic gate electrode and the gate dielectric, an on-current of the tunneling transistor is substantially improved as compared to that of a conventional tunneling transistor. In another embodiment, a tunneling transistor includes a heterostructure that reduces a turn-on voltage of the tunneling transistor.
摘要翻译：公开了隧道晶体管的几个实施例。在一个实施例中，隧道晶体管包括半导体衬底，形成在半导体衬底中的源极区域，形成在半导体衬底中的漏极区域，包括金属栅极电极和栅极电介质的栅极堆叠，以及基本上平行于金属栅极电极和栅极电介质之间的界面。作为与金属栅极电极和栅极电介质之间的界面基本平行的隧道结的结果，与常规隧道晶体管相比，隧道晶体管的导通电流显着改善。在另一个实施例中，隧道晶体管包括降低隧道晶体管的导通电压的异质结构。

36. 发明授权

US08680575B2 Semiconductor device and method of fabrication 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US08680575B2
公开(公告)日：2014-03-25
申请号：US13016888
申请日：2011-01-28
申请人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
发明人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
IPC分类号： H01L33/00
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02387 , H01L21/0245 , H01L21/02494 , H01L21/02505 , H01L21/02532 , H01L29/1075
摘要： Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
摘要翻译：本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

37. 发明授权

US08236686B2 Dual metal gates using one metal to alter work function of another metal 失效
标题翻译：双金属门使用一种金属来改变另一种金属的功能
公开(公告)号：US08236686B2
公开(公告)日：2012-08-07
申请号：US12129984
申请日：2008-05-30
申请人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
发明人： Byoung H. Lee , Sang Ho Bae , Kisik Choi , Rino Choi , Craig Huffman , Prashant Majhi , Jong Hoan Sim , Seung-Chul Song , Zhibo Zhang
IPC分类号： H01L21/44
CPC分类号： H01L21/823842 , H01L21/28088 , H01L29/4966 , H01L29/517
摘要： Methods of forming dual metal gates and the gates so formed are disclosed. A method may include forming a first metal (e.g., NMOS metal) layer on a gate dielectric layer and a second metal (e.g., PMOS metal) layer on the first metal layer, whereby the second metal layer alters a work function of the first metal layer (to form PMOS metal). The method may remove a portion of the second metal layer to expose the first metal layer in a first region; form a silicon layer on the exposed first metal layer in the first region and on the second metal layer in a second region; and form the dual metal gates in the first and second regions. Since the gate dielectric layer is continuously covered with the first metal, it is not exposed to the damage from the metal etch process.
摘要翻译：公开了形成双金属栅极和形成的栅极的方法。一种方法可以包括在第一金属层上的栅极电介质层和第二金属（例如，PMOS金属）层上形成第一金属（例如，NMOS金属）层，由此第二金属层改变第一金属的功函数层（形成PMOS金属）。该方法可以移除第二金属层的一部分以暴露第一区域中的第一金属层; 在第一区域中的暴露的第一金属层上和在第二区域中的第二金属层上形成硅层; 并在第一和第二区域形成双金属栅极。由于栅极电介质层被第一金属连续覆盖，所以不会受到金属蚀刻工艺的损害。

38. 发明申请

US20110156098A1 BUFFER STRUCTURE FOR SEMICONDUCTOR DEVICE AND METHODS OF FABRICATION 有权
标题翻译：半导体器件的缓冲结构和制造方法
公开(公告)号：US20110156098A1
公开(公告)日：2011-06-30
申请号：US13016888
申请日：2011-01-28
申请人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
发明人： Prashant Majhi , Jack Kavalieros , Wilman Tsai
IPC分类号： H01L29/12 , H01L21/20
CPC分类号： H01L29/7782 , H01L21/02381 , H01L21/02387 , H01L21/0245 , H01L21/02494 , H01L21/02505 , H01L21/02532 , H01L29/1075
摘要： Embodiments of the present invention describe a semiconductor device having an buffer structure and methods of fabricating the buffer structure. The buffer structure is formed between a substrate and a quantum well layer to prevent defects in the substrate and quantum well layer due to lattice mismatch. The buffer structure comprises a first buffer layer formed on the substrate, a plurality of blocking members formed on the first buffer layer, and second buffer formed on the plurality of blocking members. The plurality of blocking members prevent the second buffer layer from being deposited directly onto the entire first buffer layer so as to minimize lattice mismatch and prevent defects in the first and second buffer layers.
摘要翻译：本发明的实施例描述了具有缓冲结构的半导体器件和制造缓冲结构的方法。缓冲结构形成在衬底和量子阱层之间，以防止由于晶格失配而引起的衬底和量子阱层中的缺陷。缓冲结构包括形成在基板上的第一缓冲层，形成在第一缓冲层上的多个阻挡构件和形成在多个阻挡构件上的第二缓冲器。多个阻挡构件防止第二缓冲层直接沉积在整个第一缓冲层上，以便最小化晶格失配并防止第一和第二缓冲层中的缺陷。

39. 发明授权

US07687286B2 Method and apparatus for determining the thickness of a dielectric layer 有权
标题翻译：用于确定介电层厚度的方法和装置
公开(公告)号：US07687286B2
公开(公告)日：2010-03-30
申请号：US11837486
申请日：2007-08-10
申请人： Prashant Majhi
发明人： Prashant Majhi
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： G01B7/06
摘要： The method for determining the thickness of a dielectric layer according to the invention comprises the step of providing an electrically conductive body having a dielectric layer which is separated from the electrically conductive body by at least a further dielectric layer and a surface of which is exposed. Onto the exposed surface an electric charge is deposited, thereby inducing an electric potential difference between the exposed surface and the electrically conductive body. An electrical parameter relating to the electric potential difference is determined and a measurement is performed to obtain additional measurement data relating to the thickness of the dielectric layer and/or to the thickness of the further dielectric layer. In this way the thickness of the dielectric layer and/or of the further dielectric layer is determined. The method of manufacturing an electric device comprises this method for determining the thickness of a dielectric layer. The apparatus for determining the thickness of a dielectric layer is arranged to execute this method.
摘要翻译：根据本发明的用于确定电介质层的厚度的方法包括提供具有介电层的导电体的步骤，所述电介质层通过至少另外的电介质层和其表面露出而与导电体隔开。在暴露的表面上沉积电荷，从而在暴露表面和导电体之间引起电位差。确定与电位差有关的电参数，并进行测量以获得与介电层的厚度和/或另外的电介质层的厚度有关的附加测量数据。以这种方式，确定介电层和/或另外的介电层的厚度。制造电气装置的方法包括用于确定电介质层的厚度的方法。布置用于确定介电层厚度的装置来执行该方法。

40. 发明申请

US20080157171A1 DIELECTRIC BARRIER FOR NANOCRYSTALS 有权
标题翻译：用于纳米晶体的电介质阻挡层
公开(公告)号：US20080157171A1
公开(公告)日：2008-07-03
申请号：US11618666
申请日：2006-12-29
申请人： Prashant Majhi , Kyu S. Min , Wilman Tsai
发明人： Prashant Majhi , Kyu S. Min , Wilman Tsai
IPC分类号： H01L29/788 , H01L21/20
CPC分类号： H01L29/42332 , B82Y10/00 , H01L21/28273 , H01L29/513
摘要： Electronic apparatus, systems, and methods of forming such electronic apparatus and systems include non-insulating nanocrystals disposed on a dielectric stack, where the non-insulating nanocrystals are arranged to store electric charge. The dielectric stack includes two dielectric layers having different electron barriers such that the non-insulating nanocrystals may be disposed on the dielectric layer having the lower electron barrier.
摘要翻译：形成这种电子设备和系统的电子设备，系统和方法包括设置在电介质堆叠上的非绝缘纳米晶体，其中非绝缘纳米晶体被布置成存储电荷。电介质堆叠包括具有不同电子势垒的两个电介质层，使得非绝缘纳米晶体可以设置在具有较低电子势垒的电介质层上。

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