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31. 发明授权

US07929814B2 Sub-micron planar lightwave devices formed on an SOI optical platform 有权
标题翻译：在SOI光学平台上形成的亚微米平面光波器件
公开(公告)号：US07929814B2
公开(公告)日：2011-04-19
申请号：US10830571
申请日：2004-04-23
申请人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
发明人： Prakash Gothoskar , Margaret Ghiron , Robert Keith Montgomery , Vipulkumar Patel , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
IPC分类号： G02B6/10 , G02B6/12
CPC分类号： G02B6/136 , G02B6/12007 , G02B6/122 , G02B6/124 , G02B6/125 , G02B6/2813 , G02B2006/12061 , G02B2006/12097 , G02B2006/12102 , G02B2006/12104 , G02B2006/12107 , G02B2006/12147 , G02B2006/12159 , G02B2006/12173
摘要： A set of planar, two-dimensional optical devices is able to be created in a sub-micron surface layer of an SOI structure, or within a sub-micron thick combination of an SOI surface layer and an overlying polysilicon layer. Conventional masking/etching techniques may be used to form a variety of passive and optical devices in this SOI platform. Various regions of the devices may be doped to form the active device structures. Additionally, the polysilicon layer may be separately patterned to provide a region of effective mode index change for a propagating optical signal.
摘要翻译：能够在SOI结构的亚微米表面层中或在SOI表面层和上覆多晶硅层的亚微米厚度组合内产生一组平面二维光学器件。传统的掩模/蚀刻技术可用于在该SOI平台中形成各种无源和光学器件。可以掺杂器件的各个区域以形成有源器件结构。另外，多晶硅层可以被分开构图以提供传播光信号的有效模式折射率变化的区域。

32. 发明授权

US07058261B2 Interfacing multiple wavelength sources to thin optical waveguides utilizing evanescent coupling 有权
标题翻译：使用ev逝耦合将多个波长源连接到薄光波导上
公开(公告)号：US07058261B2
公开(公告)日：2006-06-06
申请号：US10935146
申请日：2004-09-07
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/34
CPC分类号： G02B6/12007 , G02B6/124 , G02B6/34
摘要： An arrangement for achieving and maintaining high efficiency coupling of light between a multi-wavelength optical signal and a relatively thin (e.g., sub-micron) silicon optical waveguide uses a prism coupler in association with an evanescent coupling layer. A grating structure having a period less than the wavelengths of transmission is formed in the coupling region (either formed in the silicon waveguide, evanescent coupling layer, prism coupler, or any combination thereof) so as to increase the effective refractive index “seen” by the multi-wavelength optical signal in the area where the beam exiting/entering the prism coupler intercepts the waveguide surface (referred to as the “prism coupling surface”). The period and/or duty cycle of the grating can be controlled to modify the effective refractive index profile in the direction away from the coupling region so as to reduce the effective refractive index from the relatively high value useful in multi-wavelength coupling to the lower value associated with maintaining confinement of the optical signals within the surface waveguide structure, thus reducing reflections along the transition region.
摘要翻译：用于实现和维持多波长光信号和较薄（例如亚微米）硅光波导之间的高效率耦合的布置使用与渐逝耦合层相关联的棱镜耦合器。在耦合区域（形成在硅波导，ev逝耦合层，棱镜耦合器或其任何组合中）形成具有小于透射波长的周期的光栅结构，以便通过“看到”来提高有效折射率离开/进入棱镜耦合器的光束截取波导表面（称为“棱镜耦合表面”）的区域中的多波长光信号。可以控制光栅的周期和/或占空比以在远离耦合区域的方向上改变有效折射率分布，以便将有效折射率从在多波长耦合中的有用折射率降低到较低的值与保持表面波导结构内的光信号的限制相关联的值，从而减少沿着过渡区域的反射。

33. 发明授权

US06968110B2 CMOS-compatible integration of silicon-based optical devices with electronic devices 有权
标题翻译：硅基光学器件与电子器件的CMOS兼容集成
公开(公告)号：US06968110B2
公开(公告)日：2005-11-22
申请号：US10828898
申请日：2004-04-21
申请人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
发明人： Vipulkumar Patel , Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Kalpendu Shastri , Soham Pathak , Katherine A. Yanushefski
IPC分类号： G02B6/12 , G02F1/025 , H01L21/77 , H01L21/84 , H01L27/12 , H01L27/13 , H01L27/146 , H01L31/12 , G02B6/10
CPC分类号： H01L27/14689 , G02B6/12004 , G02F1/025 , H01L21/84 , H01L27/1203 , H01L27/13 , H01L27/14636 , H01L27/14643 , H01L31/12
摘要： A conventional CMOS fabrication technique is used to integrate the formation of passive optical devices and active electro-optic devices with standard CMOS electrical devices on a common SOI structure. The electrical devices and optical devices share the same surface SOI layer (a relatively thin, single crystal silicon layer), with various required semiconductor layers then formed over the SOI layer. In some instances, a set of process steps may be used to simultaneously form regions in both electrical and optical devices. Advantageously, the same metallization process is used to provide electrical connections to the electrical devices and the active electro-optic devices.
摘要翻译：传统的CMOS制造技术被用于将无源光学器件和有源电光器件与标准CMOS电气器件的形成集成在公共SOI结构上。电子器件和光学器件共享相同的表面SOI层（相对薄的单晶硅层），然后在SOI层上形成各种所需的半导体层。在一些情况下，可以使用一组处理步骤来同时形成电和光学装置中的区域。有利地，使用相同的金属化工艺来提供到电气装置和主动电光装置的电连接。

34. 发明授权

US06934444B2 Beam shaping and practical methods of reducing loss associated with mating external sources and optics to thin silicon waveguides 有权
标题翻译：光束成形和减少与外部光源配合的损耗和光纤到薄硅波导的实际方法
公开(公告)号：US06934444B2
公开(公告)日：2005-08-23
申请号：US10720372
申请日：2003-11-24
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/34 , G02B6/42
CPC分类号： G02B6/425 , G02B6/34 , G02B6/4226
摘要： A practical realization for achieving and maintaining high-efficiency transfer of light from input and output free-space optics to a high-index waveguide of sub-micron thickness is described. The required optical elements and methods of fabricating, aligning, and assembling these elements are discussed. Maintaining high coupling efficiency reliably over realistic ranges of device operating parameters is discussed in the context of the preferred embodiments.
摘要翻译：描述了实现和保持从输入和输出自由空间光学器件到亚微米厚度的高折射率波导的高效率传输的实际实现。讨论了所需的光学元件和制造，对准和组装这些元件的方法。在优选实施例的上下文中讨论在设备操作参数的实际范围内可靠地维持高耦合效率。

35. 发明授权

US06917730B2 Arrangements for reducing wavelength sensitivity in prism-coupled SOI-based optical systems 有权
标题翻译：用于降低棱镜耦合的SOI基光学系统中的波长灵敏度的布置
公开(公告)号：US06917730B2
公开(公告)日：2005-07-12
申请号：US10833642
申请日：2004-04-28
申请人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
发明人： Margaret Ghiron , Prakash Gothoskar , Robert Keith Montgomery , Vipulkumar Patel , Soham Pathak , Kalpendu Shastri , Katherine A. Yanushefski
IPC分类号： G02B6/12 , G02B6/34 , G02B6/42 , G02B26/08
CPC分类号： G02B6/12 , G02B6/34 , G02B6/4206 , G02B26/0833
摘要： An optical coupling system for use with multiple wavelength optical signals provides improved coupling efficiency between a free-space optical beam and a relatively thin, surface layer of an SOI structure (“SOI layer”), allowing for sufficient coupling efficiency (greater than 50%) over a predetermined wavelength range. An evanescent coupling layer, disposed between a coupling prism and an SOI layer, is particularly configured to improve the coupling efficiency. In one embodiment, the thickness of the evanescent layer is reduced below an optimum value for a single wavelength, the reduced thickness improving coupling efficiency over a predetermined wavelength range around a defined center wavelength. Alternatively, a tapered thickness evanescent coupling layer may be used to improve coupling efficiency (or a combination of reduced thickness and tapered configuration). Optical beam steering can be combined with a modified evanescent coupling layer to control the input beam launch angle and further improve coupling efficiency.
摘要翻译：用于多波长光信号的光耦合系统提供了自由空间光束与SOI结构（“SOI层”）相对薄的表面层之间的耦合效率的提高，从而允许足够的耦合效率（大于50％）在预定波长范围内。设置在耦合棱镜和SOI层之间的渐逝耦合层特别地被配置成提高耦合效率。在一个实施例中，消逝层的厚度降低到单个波长的最佳值以下，减小的厚度提高了围绕规定的中心波长的预定波长范围的耦合效率。或者，可以使用锥形的厚度渐逝耦合层来提高耦合效率（或减小厚度和锥形配置的组合）。光束转向可以与修改的渐逝耦合层组合，以控制输入光束的发射角度，进一步提高耦合效率。

36. 发明授权

US08803269B2 Wafer scale packaging platform for transceivers 有权
标题翻译：收发器晶圆级封装平台
公开(公告)号：US08803269B2
公开(公告)日：2014-08-12
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/0232 , H01L29/40 , H01L23/053 , H01L23/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作“平台”（插入器），在其上安装或集成多个收发器模块的所有组件，硅插入器的顶表面用作参考平面，用于定义分离光学元件之间的光信号路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

37. 发明申请

US20120280344A1 Wafer Scale Packaging Platform For Transceivers 有权
标题翻译：收发器晶圆尺寸封装平台
公开(公告)号：US20120280344A1
公开(公告)日：2012-11-08
申请号：US13463408
申请日：2012-05-03
申请人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
发明人： Kalpendu Shastri , Vipulkumar Patel , Mark Webster , Prakash Gothoskar , Ravinder Kachru , Soham Pathak , Rao V. Yelamarty , Thomas Daugherty , Bipin Dama , Kaushik Patel , Kishor Desai
IPC分类号： H01L31/12
CPC分类号： H01L25/50 , G02B6/423 , G02B6/4244 , G02B6/4245 , G02B6/4249 , G02B6/4257 , G02B6/426 , H01L25/167 , H01L2224/16225 , H01L2224/48091 , H01L2224/48227 , H01L2924/00014
摘要： A wafer scale implementation of an opto-electronic transceiver assembly process utilizes a silicon wafer as an optical reference plane and platform upon which all necessary optical and electronic components are simultaneously assembled for a plurality of separate transceiver modules. In particular, a silicon wafer is utilized as a “platform” (interposer) upon which all of the components for a multiple number of transceiver modules are mounted or integrated, with the top surface of the silicon interposer used as a reference plane for defining the optical signal path between separate optical components. Indeed, by using a single silicon wafer as the platform for a large number of separate transceiver modules, one is able to use a wafer scale assembly process, as well as optical alignment and testing of these modules.
摘要翻译：光电子收发器组件过程的晶片级实现利用硅晶片作为光学参考平面和平台，同时为多个单独的收发器模块组装所有必需的光学和电子部件。特别地，硅晶片被用作平台（插入器），用于多个收发器模块的所有部件安装或集成在该平台上，硅插入器的顶表面用作用于定义光信号的参考平面分离的光学元件之间的路径。实际上，通过使用单个硅晶片作为大量单独的收发器模块的平台，可以使用晶片尺度组装过程以及这些模块的光学对准和测试。

38. 发明申请

US20050289490A1 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US20050289490A1
公开(公告)日：2005-12-29
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06G7/62
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

39. 发明授权

US07269809B2 Integrated approach for design, simulation and verification of monolithic, silicon-based opto-electronic circuits 有权
标题翻译：用于单片硅基光电路的设计，仿真和验证的综合方法
公开(公告)号：US07269809B2
公开(公告)日：2007-09-11
申请号：US11159283
申请日：2005-06-22
申请人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
发明人： Kalpendu Shastri , Soham Pathak , Prakash Gothoskar , Paulius Mosinskis , Bipin Dama
IPC分类号： G06F17/50 , G06F17/10
CPC分类号： G06F17/5036 , G06F17/5068
摘要： Computer-aided design (CAD) tools are used to perform the integrated design, verification and layout of electrical and optical components in a monolithic, silicon-based electro-optic chip. Separate top-level behavioral logic designs are prepared for the three different types of elements included within the final, silicon-based monolithic structure: (1) digital electronic integrated circuit elements; (2) analog/mixed signal electronic integrated circuit elements; and (3) opto-electronic elements (including passive and active optical elements). Once the behavioral logic design is completed, the results are combined and co-simulated. A physical layout design is developed and verified for each different type of element in the circuit. The separate physical layouts are then co-verified, to assess the properties of the overall physical design. The results of the co-simulation are compared to the results of the co-verification, with alterations made in the logic design and/or the physical layout until the desired operating parameters are obtained. Once the desired results are generated, conventional wafer-level fabrication operations are then considered to provide a final product (“tape out”).
摘要翻译：计算机辅助设计（CAD）工具用于在单片硅基电光芯片中执行电气和光学部件的集成设计，验证和布局。为最终的硅基单片结构中包含的三种不同类型的元件准备了独立的顶级行为逻辑设计：（1）数字电子集成电路元件; （2）模拟/混合信号电子集成电路元件; 和（3）光电元件（包括无源和有源光学元件）。一旦行为逻辑设计完成，结果将被合并并共同模拟。为电路中的每种不同类型的元件开发和验证物理布局设计。然后将单独的物理布局共同验证，以评估整体物理设计的属性。将共模拟的结果与协同验证的结果进行比较，在逻辑设计和/或物理布局中进行改变，直到获得所需的操作参数。一旦产生期望的结果，则常规晶圆级制造操作被认为是提供最终产品（“磁带输出”）。

40. 发明申请

US20130182996A1 Releasable Fiber Connector For Opto-Electronic Assemblies 有权
标题翻译：用于光电子组件的可释放光纤连接器
公开(公告)号：US20130182996A1
公开(公告)日：2013-07-18
申请号：US13737029
申请日：2013-01-09
申请人： Kalpendu Shastri , Soham Pathak , John Fangman , Vipulkumar Patel , Kishor Desai , Ravinder Kachru
发明人： Kalpendu Shastri , Soham Pathak , John Fangman , Vipulkumar Patel , Kishor Desai , Ravinder Kachru
IPC分类号： G02B6/42 , G02B6/12
CPC分类号： G02B6/42 , G02B6/12 , G02B6/3886 , G02B6/4214 , G02B6/4259 , G02B6/4292 , Y10T29/49155
摘要： An apparatus for providing releasable attachment between a fiber connector and an opto-electronic assembly, the opto-electronic assembly utilizing an interposer substrate to support a plurality of opto-electronic components that generates optical output signals and receives optical input signals. An enclosure is used to cover the interposer substrate and includes a transparent region through which the optical output and input signals pass unimpeded. A magnetic connector component is attached to the lid and positioned to surround the transparent region, with a fiber connector for supporting one or more optical fibers magnetically attached to the connector component by virtue of a metallic component contained in the fiber connector. This arrangement provides releasable attachment of the fiber connector to the enclosure in a manner where the optical output and input signals align with the optical fibers in the connector.
摘要翻译：一种用于在光纤连接器和光电子组件之间提供可释放附件的装置，所述光电组件利用插入器基板来支撑产生光输出信号并接收光输入信号的多个光电元件。外壳用于覆盖插入器基板，并且包括透明区域，光输出和输入信号通过该透明区域畅通无阻。磁性连接器部件附接到盖子并且被定位成围绕透明区域，光纤连接器用于通过光纤连接器中包含的金属部件来支撑一个或多个磁性地附接到连接器部件的光纤。这种布置以光输出和输入信号与连接器中的光纤对准的方式提供光纤连接器到外壳的可释放附接。

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