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31. 发明授权

US06707697B2 FAMOS type non-volatile memory 有权
标题翻译： FAMOS型非易失性存储器
公开(公告)号：US06707697B2
公开(公告)日：2004-03-16
申请号：US10126442
申请日：2002-04-19
申请人： Cyrille Dray , Richard Fournel
发明人： Cyrille Dray , Richard Fournel
IPC分类号： G11C1700
CPC分类号： G11C16/0433 , H01L27/115
摘要： An FAMOS memory includes memory cells, with each memory cell including an insulated gate transistor, and a first access transistor having a drain connected to a source of the insulated gate transistor. The FAMOS memory also includes an insulation transistor having a drain and a source respectively connected to the source of the insulated gate transistors of two adjacent cells of a same row. Each insulated gate transistor has a ring structure, and a ladder-shaped separation region insulates the cells of the same row.
摘要翻译： FAMOS存储器包括存储器单元，其中每个存储单元包括绝缘栅极晶体管，以及具有连接到绝缘栅极晶体管的源极的漏极的第一存取晶体管。 FAMOS存储器还包括绝缘晶体管，其具有分别连接到同一行的两个相邻单元的绝缘栅极晶体管的源极的漏极和源极。每个绝缘栅极晶体管具有环形结构，并且梯形分离区域使得同一行的单元绝缘。

32. 发明授权

US06580370B2 Integrated circuit with protection device 有权
公开(公告)号：US06580370B2
公开(公告)日：2003-06-17
申请号：US09895839
申请日：2001-06-29
申请人： Richard Fournel
发明人： Richard Fournel
IPC分类号： G08B1710
CPC分类号： H03K17/693 , H03K17/102
摘要： An integrated circuit receives as supply voltages a ground reference voltage, a logic supply voltage and a high voltage. A protection device is associated with at least one gate oxide circuit element. The protection device applies to a supply node of the circuit element either the logic supply voltage under normal conditions of operation of the integrated circuit, or the high voltage under abnormal conditions of operation of the integrated circuit for breaking down the gate oxide.

33. 发明授权

US06498509B2 Device to control the power supply in an integrated circuit comprising electrically programmable non-volatile memory elements 有权
公开(公告)号：US06498509B2
公开(公告)日：2002-12-24
申请号：US09896817
申请日：2001-06-29
申请人： Richard Fournel
发明人： Richard Fournel
IPC分类号： G06F738
CPC分类号： G11C5/143 , G11C16/12
摘要： An integrated circuit having as power supply voltages a low voltage reference, a logic supply voltage reference and a high voltage reference is provided. The high voltage reference is greater than the low voltage reference and the logic supply voltage reference. The integrated circuit includes an electrically programmable non-volatile memory element, and a selection and programming circuit connected thereto. A voltage control device is connected to a power supply input node of the selection and programming circuit for applying, based upon a programming control signal, the high voltage reference for programming the electrically programmable non-volatile memory element or for applying at least one logic supply voltage reference.

34. 发明授权

US6097646A Method for the testing of a dynamic memory 有权
标题翻译：动态内存测试方法
公开(公告)号：US6097646A
公开(公告)日：2000-08-01
申请号：US219470
申请日：1998-12-23
申请人： Richard Fournel
发明人： Richard Fournel
IPC分类号： G11C29/50 , G11C7/00
CPC分类号： G11C29/028 , G11C29/50 , G11C29/50016 , G11C11/401 , G11C2029/5006
摘要： A method for the testing of the retention time of a piece of information in a dynamic memory cell includes increasing the leakages of current in this cell to accelerate the loss of information. Under these testing conditions, a reduced retention time is controlled to approach the true retention time obtained under conditions of normal reading. This method makes it possible to reduce the time taken to test the retention time of the dynamic memories while at the same time being very reliable.
摘要翻译：用于测试动态存储单元中的一条信息的保留时间的方法包括增加该单元中的电流泄漏以加速信息的丢失。在这些测试条件下，减少的保留时间被控制以接近在正常读数条件下获得的真实保留时间。该方法使得可以减少测试动态存储器的保留时间所需的时间，同时非常可靠。

35. 发明授权

US5981323A Method and apparatus for protecting a device against voltage surges 失效
标题翻译：用于保护装置免受电压浪涌的方法和装置
公开(公告)号：US5981323A
公开(公告)日：1999-11-09
申请号：US854840
申请日：1997-05-12
申请人： Richard Fournel , Fabrice Marinet
发明人： Richard Fournel , Fabrice Marinet
IPC分类号： H01L27/02 , H01L21/8238
CPC分类号： H01L27/0259
摘要： A structure for the protection of a high-voltage pad includes a lateral bipolar transistor, an N-type diffusion of which, connected to the pad to be protected, is made in an N-type tub with a zone that extends laterally outside the tub in the base. A P-type implantation is made on the entire substrate outside the N-type tub except in the region in which the zone extends.
摘要翻译：用于保护高压焊盘的结构包括横向双极晶体管，其N型扩散连接到待保护焊盘的N型扩散件制成在具有横向外延伸到槽体的区域的N型槽中在基地。除了区域延伸的区域外，在N型桶外的整个基板上进行P型注入。

36. 发明授权

US07298643B2 MRAM element 有权
标题翻译： MRAM元素
公开(公告)号：US07298643B2
公开(公告)日：2007-11-20
申请号：US11114305
申请日：2005-04-25
申请人： Joo-Von Kim , Thibaut Devolder , Claude Chappert , Cedric Maufront , Richard Fournel
发明人： Joo-Von Kim , Thibaut Devolder , Claude Chappert , Cedric Maufront , Richard Fournel
IPC分类号： G11C11/00
CPC分类号： G11C11/16
摘要： A magnetoresistive memory element including a trapped magnetic region and a free magnetic region separated by a barrier layer. The free magnetic region comprises a stacking of at least two antiferromagnetically-coupled ferromagnetic layers, a layer magnetic moment vector being associated with each layer, the resulting magnetic moment vector, equal to the sum of the layer magnetic moment vectors, having an amplitude smaller than at least 40% of the amplitude of the layer magnetic moment vector of maximum amplitude. The anisotropy field and/or the demagnetizing field tensor is not identical for the at least two ferromagnetic layers, whereby the angular deviations of the layer magnetic moment vectors are different at the time of the application of an external magnetic field, which enables at least two methods for directly writing into the memory element, as well as its initialization.
摘要翻译：一种磁阻存储元件，包括被阻挡层分离的被俘获的磁区和自由磁区。自由磁区包括至少两个反铁磁耦合铁磁层的层叠，与每个层相关联的层磁矩矢量，所得到的磁矩矢量等于具有振幅小于的磁矩矢量的和至少40％的振幅最大振幅的磁矩矢量。对于至少两个铁磁层，各向异性场和/或去磁场张量不相同，由此在施加外部磁场时层磁矩矢量的角度偏差是不同的，这使得能够至少两个直接写入存储器元件的方法，以及它的初始化。

37. 发明申请

US20070189066A1 Magnetic Random Access Memory Array Having Bit/Word Lines for Shared Write Select and Read Operations 有权
标题翻译：具有用于共享写入选择和读取操作的位/字线的磁性随机存取存储器阵列
公开(公告)号：US20070189066A1
公开(公告)日：2007-08-16
申请号：US11738987
申请日：2007-04-23
申请人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sebastien Barasinski , Richard Fournel
发明人： Cyrille Dray , Christophe Frey , Jean Lasseuguette , Sebastien Barasinski , Richard Fournel
IPC分类号： G11C11/14
CPC分类号： G11C11/15
摘要： A random access memory array includes random access memory elements arranged in a rows and columns. The elements of each row have a word line and a write digit line and the elements of each column have a bit line and a write bit line. A first selection circuit/transistor for each row has a first source-drain path coupled in the write digit line and a gate terminal coupled to the word line. A second selection circuit/transistor for each column has a second source-drain path coupling in the write bit line and a gate terminal coupled to the bit line. A first write signal is applied to one word line to actuate the first selection circuit/transistor for the row corresponding to that one word line and cause a write current to flow through the first source-drain path of the actuated first selection circuit/transistor and the corresponding write digit line to write data into certain memory elements in that row. A second write signal is applied to one bit line to actuate the second selection circuit/transistor for the column corresponding to that one bit line and cause a write current to flow through the second source-drain path of the actuated second selection circuit/transistor and the corresponding write bit line to write data into at least one memory element in that column.
摘要翻译：随机存取存储器阵列包括排列成行和列的随机存取存储器元件。每行的元素具有字线和写数字线，并且每列的元素具有位线和写位线。用于每行的第一选择电路/晶体管具有耦合在写入数字线中的第一源极 - 漏极通路和耦合到字线的栅极端子。用于每列的第二选择电路/晶体管具有在写位线中耦合的第二源 - 漏路径和耦合到位线的栅极端。第一写入信号被施加到一个字线以激活对应于该一条字线的行的第一选择电路/晶体管，并且使得写入电流流过被激活的第一选择电路/晶体管的第一源极 - 漏极路径，并且相应的写数字行将数据写入该行中的某些存储器元素。第二写入信号被施加到一个位线以启动与该一个位线相对应的列的第二选择电路/晶体管，并且使得写入电流流过被致动的第二选择电路/晶体管的第二源极 - 漏极通路，并且相应的写位线将数据写入该列中的至少一个存储器元件。

38. 发明授权

US07167036B2 Circuit for transforming signals varying between different voltages 有权
标题翻译：用于转换不同电压之间变化的信号的电路
公开(公告)号：US07167036B2
公开(公告)日：2007-01-23
申请号：US10915248
申请日：2004-08-09
申请人： Richard Fournel
发明人： Richard Fournel
IPC分类号： H03L5/00
CPC分类号： H03K19/0013 , H03K19/018521
摘要： An interface circuit for transforming a first signal varying between a low voltage and a high voltage into a second signal varying between a lower voltage and a higher voltage, the lower voltage being smaller than the low voltage and/or the higher voltage being greater than the high voltage, comprising: an inverter circuit receiving the first signal and being connected for its supply between said higher voltage and said lower voltage, one at least of these connections being performed via at least one diode, a conversion element supplied between said higher and lower voltages, and receiving the output of the inverter circuit and providing the second signal, a storage element capable of maintaining the output of the inverter circuit at said higher or lower voltage when the first signal is respectively equal to the low or high voltage.
摘要翻译：一种用于将在低电压和高电压之间变化的第一信号变换成在较低电压和较高电压之间变化的第二信号的接口电路，所述较低电压小于所述低电压和/或所述较高电压大于高电压，包括：反相器电路，接收所述第一信号，并且在所述较高电压和所述较低电压之间连接供电，所述至少一个连接通过至少一个二极管执行，所述转换元件在所述较高和较低电压之间提供电压，并且接收逆变器电路的输出并提供第二信号，当第一信号分别等于低电压或高电压时，能够将逆变器电路的输出保持在所述较高或较低电压的存储元件。

39. 发明授权

US06940119B2 Non-volatile programmable and electrically erasable memory with a single layer of gate material 有权
标题翻译：具有单层栅极材料的非易失性可编程和电可擦除存储器
公开(公告)号：US06940119B2
公开(公告)日：2005-09-06
申请号：US10383153
申请日：2003-03-06
申请人： Cyrille Dray , Phillipe Gendrier , Richard Fournel
发明人： Cyrille Dray , Phillipe Gendrier , Richard Fournel
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788 , H01L29/792 , H01L29/76
CPC分类号： H01L27/11521 , H01L27/115 , H01L27/11558 , H01L29/66825 , H01L29/7883
摘要： The semiconducting memory device comprises a non-volatile programmable and electrically erasable memory cell with a single layer of grid material and comprising a floating grid transistor and a control grid, within an active semiconducting area formed in a region of the substrate and delimited by an isolation region. The layer of grid material EG, FL P2 in which the floating grid FG is made extends integrall above the active area ZA without overlapping part of the isolation region STI, and the transistor is electrically isolated from the control grid CG by PN junctions that will be reverse biased.
摘要翻译：半导体存储器件包括具有单层栅格材料的非易失性可编程和电可擦除存储器单元，并且包括浮动栅格晶体管和控制栅格，该栅极晶体管和控制栅极位于形成在衬底的区域中且由隔离区限定的有源半导体区域内地区。形成浮栅FG的栅格材料EG，FLP2层在有源区ZA之上扩展而不与隔离区STI重叠，并且晶体管通过PN结与控制栅格CG电绝缘，PN结反向偏置。

40. 发明授权

US06778440B2 Method and device for checking a group of cells in a non-volatile memory cells 有权
标题翻译：用于检查非易失性存储器中的一组单元的方法和装置
公开(公告)号：US06778440B2
公开(公告)日：2004-08-17
申请号：US10363234
申请日：2003-03-05
申请人： Richard Fournel , Leila Sedjai Aitouarab
发明人： Richard Fournel , Leila Sedjai Aitouarab
IPC分类号： G11C1606
CPC分类号： G11C16/3436 , G11C29/34
摘要： An electrical state of a group of N cells of a non-volatile memory are simultaneously checked. The group of N memory cells to be checked, along with a checking cell, are simultaneously selected and read. The N signals read are summed to obtain a summed signal. The summed signal is compared with the signal read from the checking cell to-provide a first state signal when the summed signal is less than the signal read from the checking cell. This indicates that the N memory cells are in a first electrical state. If a second state signal is provided in the comparison, this indicates that at least one memory cell is not in the first electrical state when the summed signal is greater than the signal read on the checking cell.
摘要翻译：同时检查非易失性存储器的一组N个单元的电气状态。要检查的N个存储单元的组与检查单元一起被同时选择和读取。将N个信号读取相加以获得加和信号。将总和信号与从检查单元读取的信号进行比较，以在求和信号小于从检查单元读取的信号时提供第一状态信号。这表示N个存储单元处于第一电状态。如果在比较中提供第二状态信号，则这指示当相加的信号大于在检查单元上读取的信号时，至少一个存储单元不处于第一电状态。

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