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31. 发明授权

US07944931B2 Balanced bandwidth utilization 失效
标题翻译：平衡带宽利用率
公开(公告)号：US07944931B2
公开(公告)日：2011-05-17
申请号：US11776162
申请日：2007-07-11
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/28 , H04J3/24
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：存储器子系统包括数据存储0和数据存储1.每个数据存储分区为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二个格式从Data Store 1中选择第一个缓冲区，并从Data Store 0中选择一个第二个缓冲区。控制器选择一个用于存储数据的缓冲区基于诸如交换单元之类的递送机制中的数据的配置。

32. 发明授权

US07937533B2 Structure for handling data requests 失效
标题翻译：处理数据请求的结构
公开(公告)号：US07937533B2
公开(公告)日：2011-05-03
申请号：US12114792
申请日：2008-05-04
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/00 , G06F13/00
CPC分类号： G06F12/0815 , G06F2212/507
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a memory controller, memory, a bus connecting the CPU, memory controller and memory, circuitry for providing a speculative read threshold corresponding to a selected percentage of the total number of reads that can be speculatively issued, and circuitry for intermixing demand reads and speculative reads in accordance with the speculative read threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储器控制器，存储器，连接CPU，存储器控制器和存储器的总线，用于提供与可读取总数的所选百分比相对应的推测读取阈值的电路推测性发布，以及根据推测读取阈值混合需求读取和推测读取的电路。

33. 发明授权

US07660952B2 Data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 失效
标题翻译：在可变延迟模式下工作的FBDIMM存储系统中的数据总线带宽调度
公开(公告)号：US07660952B2
公开(公告)日：2010-02-09
申请号：US11680695
申请日：2007-03-01
申请人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
IPC分类号： G06F12/06
CPC分类号： G06F13/4243
摘要： A method and system for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system. A scheduling algorithm pre-computes return time data for data connected to all DRAM buffer chips and stores the return time data in a table. The return time data is expressed as a set of data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector representing a compilation of data return time vectors of all executing requests to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译：一种用于在FBDIMM存储器子系统中使用可变等待时间模式来调度数据请求的服务的方法和系统。调度算法预先计算连接到所有DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。返回时间数据表示为在每个向量中一位等于“1”的一组数据返回时间二进制向量。对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。此外，调度算法利用表示所有执行请求的数据返回时间向量的汇编的更新历史向量，以确定接收到的请求是否对执行请求产生冲突。通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。

34. 发明授权

US07657771B2 Method and apparatus for reducing latency associated with read operations in a memory system 失效
标题翻译：用于减少与存储器系统中的读取操作相关联的延迟的方法和装置
公开(公告)号：US07657771B2
公开(公告)日：2010-02-02
申请号：US11621201
申请日：2007-01-09
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F1/04 , G06F13/00
CPC分类号： G06F13/1689
摘要： Methods and system for reducing latency associated with a read operation in a processor memory system are provided. In one implementation, the method includes receiving an early indicator corresponding to read data from a memory, delaying the early indicator in accordance with a pre-determined delay such that the early read indicator is passed to a bus in advance of the read data; and dynamically adjusting the pre-determined delay using an adjustment delay circuit, the pre-determined delay being adjusted responsive to a change in operational speed of the bus or change in operational speed of a processor coupled to the bus.
摘要翻译：提供了用于减少与处理器存储器系统中的读取操作相关联的延迟的方法和系统。在一个实现中，该方法包括从存储器接收对应于读取数据的早期指示符，根据预定延迟延迟早期指示符，使得早期读取指示符在读取数据之前被传递到总线; 以及使用调整延迟电路动态调整预定延迟，响应于总线的操作速度的变化或耦合到总线的处理器的操作速度的改变来调整预定的延迟。

35. 发明申请

US20090150618A1 STRUCTURE FOR HANDLING DATA ACCESS 失效
标题翻译：处理数据访问的结构
公开(公告)号：US20090150618A1
公开(公告)日：2009-06-11
申请号：US12115146
申请日：2008-05-05
申请人： James J. Allen, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, JR. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/02
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路根据投机访问阈值访问和推测访问。

36. 发明申请

US20080240110A1 MEMORY SYSTEM WITH APPARATUS AND METHOD TO ENABLE BALANCED BANDWIDTH UTILIZATION 失效
标题翻译：具有装置的存储系统和使用平衡带宽利用的方法
公开(公告)号：US20080240110A1
公开(公告)日：2008-10-02
申请号：US11776162
申请日：2007-07-11
申请人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
发明人： Brian M. Bass , Gordon T. Davis , Michael S. Siegel , Michael R. Trombley
IPC分类号： H04L12/56
CPC分类号： H04L49/9042 , H04L49/90 , H04L2012/5681
摘要： A memory subsystem includes Data Store 0 and Data Store 1. Each data store is partitioned into N buffers, N>1. An increment of memory is formed by a buffer pair, with each buffer of the buffer pair being in a different data store. Two buffer pair formats are used in forming memory increments. A first format selects a first buffer from Data Store 0 and a second buffer from Data Store 1, while a second format selects a first buffer from Data Store 1 and a second buffer from Data Store 0. A controller selects a buffer pair for storing data based upon the configuration of data in a delivery mechanism, such as switch cell.
摘要翻译：内存子系统包括数据存储0和数据存储1。每个数据存储区分为N个缓冲区，N> 1。存储器的增量由缓冲器对形成，缓冲器对的每个缓冲器在不同的数据存储器中。两个缓冲器对格式用于形成存储器增量。第一种格式从Data Store 0中选择第一个缓冲区，从Data Store 1中选择第二个缓冲区，而第二种格式从Data Store 1中选择第一个缓冲区，从Data Store 0中选择第二个缓冲区。控制器基于诸如交换单元之类的传送机制中的数据的配置来选择用于存储数据的缓冲器对。

37. 发明申请

US20080209095A1 STRUCTURE FOR REDUCING LATENCY ASSOCIATED WITH READ OPERATIONS IN A MEMORY SYSTEM 失效
标题翻译：用于减少与存储器系统中的读操作相关的延迟的结构
公开(公告)号：US20080209095A1
公开(公告)日：2008-08-28
申请号：US12114787
申请日：2008-05-04
申请人： JAMES J. ALLEN , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： JAMES J. ALLEN , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F13/36
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a processor memory system, which may include a processor and a memory controller in communication with the processor through a bus. The memory controller may include a delay circuit to receive an early read indicator corresponding to read data from a memory, the delay circuit to delay the early read indicator in accordance with a pre-determined delay such that the early read indicator is passed to the bus in advance of the read data, and a delay adjustment circuit to dynamically adjust the pre-determined delay associated with the delay circuit responsive to a change in operational speed of the processor or the bus.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。设计结构通常包括处理器存储器系统，其可以包括处理器和通过总线与处理器通信的存储器控制器。存储器控制器可以包括延迟电路，用于接收对应于来自存储器的读取数据的早期读取指示符，延迟电路根据预定的延迟来延迟早期读取指示符，使得早期读取指示符被传递到总线以及延迟调整电路，用于响应于处理器或总线的操作速度的变化来动态地调整与延迟电路相关联的预定延迟。

38. 发明授权

US5471626A Variable stage entry/exit instruction pipeline 失效
标题翻译：变量进入/退出指令流水线
公开(公告)号：US5471626A
公开(公告)日：1995-11-28
申请号：US879651
申请日：1992-05-06
申请人： Michael J. Carnevale , Ronald N. Kalla , Gary P. McClannahan , Michael R. Trombley
发明人： Michael J. Carnevale , Ronald N. Kalla , Gary P. McClannahan , Michael R. Trombley
IPC分类号： G06F9/28 , G06F9/38
CPC分类号： G06F9/3873 , G06F9/3867
摘要： An instruction pipeline includes a sequence of interconnected pipeline stages, each stage dedicated to one of several operations executed on data in a digital processing device. Control words govern execution of the operations as they progress through the pipeline. The pipeline stages, as well as the pipeline entry and exit, are interconnected in a manner that permits each control word to enter and exit the pipeline at any one of the stages, and to skip any stages in which the control word will not govern any operations on data. On occasion, this permits a control word to bypass another control word which originally preceded it in the pipeline, thus to reverse the order of the two control words. A mapping field in each control word predetermines its route through the instruction pipeline, one bit of the map field corresponding to each pipeline stage. The route of each control word further is controlled by arbitration logic to resolve contentions among control words for particular pipeline stages, and to insure against a reversal in control word order when such reversal might produce an error. Each pipeline stage is a data register configured to accommodate one control word at a time. Succeeding stage registers are selectively reduced in length to eliminate selected segments and bit positions, thereby deleting from each control word certain bits and multiple bit fields executed in preceding stages.
摘要翻译：指令流水线包括一系列互连的流水线级，各级专用于在数字处理装置中对数据执行的若干操作之一。控制字管理操作在管道进行时的执行。流水线阶段以及管道进出口以允许每个控制字在任何一个阶段进入和退出管道的方式相互连接，并且跳过控制字不管理任何阶段的任何阶段数据操作。有时，这允许一个控制字绕过原来在其前面的另一个控制字，从而颠倒两个控制字的顺序。每个控制字中的映射字段预先确定其通过指令流水线的路由，对应于每个流水线级的映射字段的一位。每个控制字的路由进一步由仲裁逻辑控制，以解决特定流水线级的控制字之间的争用，并且当这种反转可能产生错误时，确保防止控制字顺序的反转。每个流水线级是配置为一次容纳一个控制字的数据寄存器。成功的级寄存器被选择性地减小长度以消除所选择的段和位位置，从而从每个控制字删除某些位和在先前阶段执行的多个位字段。

39. 发明授权

US08032713B2 Structure for handling data access 失效
标题翻译：用于处理数据访问的结构
公开(公告)号：US08032713B2
公开(公告)日：2011-10-04
申请号：US12115146
申请日：2008-05-05
申请人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , James A. Mossman , Michael R. Trombley
IPC分类号： G06F12/00
CPC分类号： G06F12/0862
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design is provided. The design structure generally includes a computer system that includes a CPU, a storage device, circuitry for providing a speculative access threshold corresponding to a selected percentage of the total number of accesses to the storage device that can be speculatively issued, and circuitry for intermixing demand accesses and speculative accesses in accordance with the speculative access threshold.
摘要翻译：提供了体现在用于设计，制造和/或测试设计的机器可读存储介质中的设计结构。该设计结构通常包括计算机系统，其包括CPU，存储设备，用于提供与可推测发布的对存储设备的访问总数的所选百分比相对应的推测访问阈值的电路，以及用于混合需求的电路根据投机访问阈值访问和推测访问。

40. 发明授权

US08028257B2 Structure for data bus bandwidth scheduling in an FBDIMM memory system operating in variable latency mode 有权
标题翻译：在可变延迟模式下工作的FBDIMM存储器系统中数据总线带宽调度的结构
公开(公告)号：US08028257B2
公开(公告)日：2011-09-27
申请号：US12110765
申请日：2008-04-28
申请人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
发明人： James J. Allen, Jr. , Steven K. Jenkins , Michael R. Trombley
IPC分类号： G06F17/50 , G06F12/06 , G06F13/00
CPC分类号： G06F13/1689
摘要： A design structure embodied in a machine readable storage medium for designing, manufacturing, and/or testing a design for scheduling the servicing of data requests, using the variable latency mode, in an FBDIMM memory sub-system is provided. A scheduling algorithm pre-computes return time data for data connected to DRAM buffer chips and stores the return time data in a table. The return time data is expressed as data return time binary vectors with one bit equal to “1” in each vector. For each received data request, the memory controller retrieves the appropriate return time vector. Additionally, the scheduling algorithm utilizes an updated history vector to determine whether the received request presents a conflict to the executing requests. By computing and utilizing a score for each request, the scheduling algorithm re-orders and schedules the execution of selected requests to preserve as much data bus bandwidth as possible, while avoiding conflict.
摘要翻译：提供了一种体现在机器可读存储介质中的设计结构，用于在FBDIMM存储器子系统中使用可变延迟模式来设计，制造和/或测试用于调度数据请求的服务的设计。调度算法预先计算连接到DRAM缓冲器芯片的数据的返回时间数据，并将返回时间数据存储在表中。返回时间数据表示为在每个向量中一位等于“1”的数据返回时间二进制向量。对于每个接收到的数据请求，存储器控制器检索适当的返回时间向量。此外，调度算法利用更新的历史向量来确定接收到的请求是否对执行请求产生冲突。通过计算和利用每个请求的分数，调度算法重新排序和调度所选择的请求的执行，以尽可能地保留尽可能多的数据总线带宽，同时避免冲突。

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