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31. 发明申请

US20080141268A1 UTILITY FUNCTION EXECUTION USING SCOUT THREADS 审中-公开
标题翻译：使用SCOUT螺纹的实用功能执行
公开(公告)号：US20080141268A1
公开(公告)日：2008-06-12
申请号：US11609682
申请日：2006-12-12
申请人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
发明人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
IPC分类号： G06F9/46
CPC分类号： G06F9/4843
摘要： A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. The first and second threads are configured to operate in a producer-consumer relationship. The second thread is configured to execute utility type functions in advance of the first thread reaching the functions in the program code. The second thread executes in parallel with the first thread and produces results from the execution which are made available for consumption by the first thread. Analysis of the program code is performed to identify such utility functions and modify the program code to support execution of the functions by the second thread.
摘要翻译：一种在计算系统中使用线程的方法和机制。多线程计算系统被配置为执行第一线程和第二线程。第一和第二线程被配置为在生产者 - 消费者关系中操作。第二线程被配置为在第一线程达到程序代码中的功能之前执行实用程序类型功能。第二个线程与第一个线程并行执行，并产生执行的结果，这些结果可供第一个线程使用。执行程序代码的分析以识别这种效用函数并修改程序代码以支持第二线程执行功能。

32. 发明授权

US08595744B2 Anticipatory helper thread based code execution 有权
标题翻译：基于预期的助手线程代码执行
公开(公告)号：US08595744B2
公开(公告)日：2013-11-26
申请号：US11436948
申请日：2006-05-18
申请人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
发明人： Partha P. Tirumalai , Yonghong Song , Spiros Kalogeropulos
IPC分类号： G06F9/46
CPC分类号： G06F9/4843 , G06F9/52
摘要： A method and mechanism for using threads in a computing system. A multithreaded computing system is configured to execute a first thread and a second thread. Responsive to the first thread detecting a launch point for a function, the first thread is configured to provide an indication to the second thread that the second thread may begin execution of a given function. The launch point of the function precedes an actual call point of the function in an execution sequence. The second thread is configured to initiate execution of the function in response to the indication. The function includes one or more inputs and the second thread uses anticipated values for each of the one or more inputs. When the first thread reaches a call point for the function, the first thread is configured to use a results of the second thread's execution, in response to determining the anticipated values used by the second thread were correct.
摘要翻译：一种在计算系统中使用线程的方法和机制。多线程计算系统被配置为执行第一线程和第二线程。响应于检测功能的发起点的第一线程，第一线程被配置为向第二线程提供指示第二线程可以开始执行给定功能的指示。该功能的启动点在执行顺序中的函数的实际调用点之前。第二线程被配置为响应于该指示来启动该功能的执行。该功能包括一个或多个输入，第二线程使用一个或多个输入中的每一个的预期值。当第一线程到达功能的调用点时，第一线程被配置为使用第二线程的执行结果，以响应于确定第二线程使用的预期值是正确的。

33. 发明授权

US08312442B2 Method and system for interprocedural prefetching 有权
标题翻译：进程间预取的方法和系统
公开(公告)号：US08312442B2
公开(公告)日：2012-11-13
申请号：US12331999
申请日：2008-12-10
申请人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F8/456
摘要： A computing system has an amount of shared cache, and performs runtime automatic parallelization wherein when a parallelized loop is encountered, a main thread shares the workload with at least one other non-main thread. A method for providing interprocedural prefetching includes compiling source code to produce compiled code having a main thread including a parallelized loop. Prior to the parallelized loop in the main thread, the main thread includes prefetching instructions for the at least one other non-main thread that shares the workload of the parallelized loop. As a result, the main thread prefetches data into the shared cache for use by the at least one other non-main thread.
摘要翻译：计算系统具有一定数量的共享缓存，并且执行运行时自动并行化，其中当遇到并行循环时，主线程与至少一个其他非主线程共享工作负载。提供过程间预取的方法包括编译源代码以产生具有包括并行化循环的主线程的编译代码。在主线程中的并行循环之前，主线程包括用于共享并行化循环的工作负载的至少一个其他非主线程的预取指令。结果，主线程将数据预取到共享高速缓存中以供至少一个其他非主线程使用。

34. 发明授权

US08151252B2 Compiler framework for speculative automatic parallelization with transactional memory 有权
标题翻译：用于使用事务性内存进行投机自动并行化的编译器框架
公开(公告)号：US08151252B2
公开(公告)日：2012-04-03
申请号：US12035828
申请日：2008-02-22
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45
CPC分类号： G06F9/3863 , G06F8/456 , G06F9/3842 , G06F9/3851
摘要： A computer program is speculatively parallelized with transactional memory by scoping program variables at compile time, and inserting code into the program at compile time. Determinations of the scoping can be based on whether scalar variables being scoped are involved in inter-loop non-reduction data dependencies, are used outside loops in which they were defined, and at what point in a loop a scalar variable is defined. The inserted code can include instructions for execution at a run time of the program to determine loop boundaries of the program, and issue checkpoint instructions and commit instructions that encompass transaction regions in the program. A transaction region can include an original function of the program and a spin-waiting loop with a non-transactional load, wherein the spin-waiting loop is configured to wait for a previous thread to commit before the current transaction commits.
摘要翻译：计算机程序通过在编译时对程序变量进行范围划分，并在编译时将代码插入到程序中，通过事务性存储器推测并行化。范围界定的确定可以基于范围变量是否涉及到循环中的非还原数据依赖关系，它们被定义在外部循环中，以及在循环中什么时候定义标量变量。插入的代码可以包括用于在程序运行时执行的指令以确定程序的循环边界，以及发出检查点指令并提交包含程序中的事务区域的指令。事务区域可以包括程序的原始功能和具有非事务负载的自转等待循环，其中，所述旋转等待循环被配置为在当前事务提交之前等待先前线程提交。

35. 发明申请

US20100325618A1 FAULT TOLERANT COMPILATION WITH AUTOMATIC ERROR CORRECTION 有权
标题翻译：具有自动错误校正的容错编译
公开(公告)号：US20100325618A1
公开(公告)日：2010-12-23
申请号：US12488710
申请日：2009-06-22
申请人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/45 , G06F11/07
CPC分类号： G06F8/43 , G06F8/443 , G06F11/3624
摘要： A compilation method is provided for automated user error correction. The method includes using a compiler driver run by a processor to receive a source file for compilation. With a compiler component invoked by the compiler driver, the method includes identifying an error in the source file such as a linking problem or syntax error in the user's program. The method includes receiving with the compiler driver an error message corresponding to the identified error. With an error corrector module run by the processor, the method includes processing the error message to determine an error correction for the identified error in the source file. The compiler driver modifies the source file based on the error correction and compiles the modified source file with the compiler component.
摘要翻译：提供了自动化用户错误校正的编译方法。该方法包括使用由处理器运行的编译器驱动程序接收源文件进行编译。使用由编译器驱动程序调用的编译器组件，该方法包括识别源文件中的错误，例如用户程序中的链接问题或语法错误。该方法包括使用编译器驱动程序接收与所识别的错误相对应的错误消息。使用由处理器运行的错误校正器模块，该方法包括处理错误消息以确定源文件中识别的错误的错误校正。编译器驱动程序根据纠错修改源文件，并使用编译器组件编译修改的源文件。

36. 发明申请

US20100153959A1 CONTROLLING AND DYNAMICALLY VARYING AUTOMATIC PARALLELIZATION 有权
标题翻译：控制和动态变化自动并行
公开(公告)号：US20100153959A1
公开(公告)日：2010-06-17
申请号：US12335124
申请日：2008-12-15
申请人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/50
CPC分类号： G06F9/485
摘要： A system and method for automatically controlling run-time parallelization of a software application. A buffer is allocated during execution of program code of an application. When a point in program code near a parallelized region is reached, demand information is stored in the buffer in response to reaching a predetermined first checkpoint. Subsequently, the demand information is read from the buffer in response to reaching a predetermined second checkpoint. Allocation information corresponding to the read demand information is computed and stored the in the buffer for the application to later access. The allocation information is read from the buffer in response to reaching a predetermined third checkpoint, and the parallelized region of code is executed in a manner corresponding to the allocation information.
摘要翻译：一种用于自动控制软件应用程序运行时并行化的系统和方法。在执行应用程序代码期间分配缓冲区。当到达并行化区域附近的程序代码点时，响应于到达预定的第一检查点，请求信息被存储在缓冲器中。随后，响应于到达预定的第二检查点，从缓冲器读取需求信息。计算与读请求信息相对应的分配信息，并将其存储在用于应用的缓冲器中以供稍后访问。响应于到达预定的第三检查点，从缓冲器读取分配信息，并且以对应于分配信息的方式执行并行化的代码区域。

37. 发明申请

US20090276758A1 STATIC PROFITABILITY CONTROL FOR SPECULATIVE AUTOMATIC PARALLELIZATION 有权
标题翻译：用于统计自动并行的静态利润控制
公开(公告)号：US20090276758A1
公开(公告)日：2009-11-05
申请号：US12113716
申请日：2008-05-01
申请人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/44
CPC分类号： G06F8/456
摘要： A compilation method and mechanism for parallelizing program code. A method for compilation includes analyzing source code and identifying candidate code for parallelization. Having identified one or more suitable candidates, the profitability of parallelizing the candidate code is determined. If the profitability determination meets a predetermined criteria, then the candidate code may be parallelized. If, however, the profitability determination does not meet the predetermined criteria, then the candidate code may not be parallelized. Candidate code may comprises a loop, and determining profitability of parallelization may include computing a probability of transaction failure for the loop. Additionally, a determination of an execution time of a parallelized version of the loop is made. If the determined execution time is less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may be parallelized. If the determined execution time is not less than an execution time of a non-parallelized version of said loop by at least a given amount, then the loop may not be parallelized.
摘要翻译：用于并行化程序代码的编译方法和机制。一种编译方法包括分析源代码和识别用于并行化的候选代码。确定了一个或多个合适的候选者后，确定并行化候选代码的盈利能力。如果盈利能力确定满足预定标准，则候选代码可以并行化。然而，如果盈利能力确定不符合预定标准，则候选代码可能不并行化。候选代码可以包括循环，并且确定并行化的获利能力可以包括计算循环的事务失败概率。此外，进行环路的并行化版本的执行时间的确定。如果确定的执行时间小于所述循环的非并行化版本的执行时间至少给定量，则可以并行化该循环。如果确定的执行时间不小于所述循环的非并行化版本的执行时间至少给定量，则循环可能不并行化。

38. 发明申请

US20090235237A1 VALUE PREDICTABLE VARIABLE SCOPING FOR SPECULATIVE AUTOMATIC PARALLELIZATION WITH TRANSACTIONAL MEMORY 有权
标题翻译：用于具有可交互存储器的自动并行自动平均值的可预测可变范围
公开(公告)号：US20090235237A1
公开(公告)日：2009-09-17
申请号：US12046365
申请日：2008-03-11
申请人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
发明人： Yonghong Song , Xiangyun Kong , Spiros Kalogeropulos , Partha P. Tirumalai
IPC分类号： G06F9/44
CPC分类号： G06F8/456
摘要： Parallelize a computer program by scoping program variables at compile time and inserting code into the program. Identify as value predictable variables, variables that are: defined only once in a loop of the program; not defined in any inner loop of the loop; and used in the loop. Optionally also: identify a code block in the program that contains a variable assignment, and then traverse a path backwards from the block through a control flow graph of the program. Name in a set all blocks along the path until a loop header block. For each block in the set, determine program blocks that logically succeed the block and are not in the first set. Identify all paths between the block and the determined blocks as failure paths, and insert code into the failure paths. When executed at run time of the program, the inserted code fails the corresponding path.
摘要翻译：通过在编译时对程序变量进行范围并将代码插入程序来并行化计算机程序。识别为值可预测变量，变量是：在程序循环中仅定义一次; 没有在循环的任何内循环中定义; 并在循环中使用。还可以：识别包含变量赋值的程序中的代码块，然后通过程序的控制流程图从块向后移动一个路径。命名一个路径中的所有块，直到循环头块。对于集合中的每个块，确定在块上逻辑成功并且不在第一组中的程序块。将块和确定的块之间的所有路径标识为故障路径，并将代码插入故障路径。当在程序的运行时执行时，插入的代码失败相应的路径。

39. 发明申请

US20070283105A1 Method and system for identifying multi-block indirect memory access chains 有权
标题翻译：用于识别多块间接存储器访问链的方法和系统
公开(公告)号：US20070283105A1
公开(公告)日：2007-12-06
申请号：US11446624
申请日：2006-06-05
申请人： Spiros Kalogeropulos , Yonghong Song , Partha P. Tirumalai
发明人： Spiros Kalogeropulos , Yonghong Song , Partha P. Tirumalai
IPC分类号： G06F13/00 , G06F12/00
CPC分类号： G06F12/0862 , G06F2212/6028
摘要： A method and system for identifying multi-block indirect memory access chains. A method may include identifying basic blocks between an entry point and an exit point of a procedure, where the procedure includes a control statement governing its execution. It may be determined whether a probability of execution of a given basic block relative to the control statement equals or exceeds a first threshold value. If so, a respective set of one or more chains of indirect memory accesses may be generated, where each chain includes at least a respective head memory access that does not depend for its memory address computation on another memory access within the given basic block. Chains may be joined across basic blocks dependent upon whether the relative execution probabilities of the blocks exceed a threshold value.
摘要翻译：一种用于识别多块间接存储器访问链的方法和系统。方法可以包括识别过程的入口点和出口点之间的基本块，其中过程包括管理其执行的控制语句。可以确定给定基本块相对于控制语句的执行概率是否等于或超过第一阈值。如果是这样，则可以生成一组或多个间接存储器访问链，其中每个链包括至少一个相应的头部存储器访问，其不依赖于其在给定基本块内的另一个存储器访问上的存储器地址计算。可以根据块的相对执行概率是否超过阈值，跨基本块连接链。

40. 发明授权

US07234136B2 Method and apparatus for selecting references for prefetching in an optimizing compiler 有权
标题翻译：用于在优化编译器中选择用于预取的参考的方法和装置
公开(公告)号：US07234136B2
公开(公告)日：2007-06-19
申请号：US10052997
申请日：2001-11-02
申请人： Partha P Tirumalai , Spiros Kalogeropulos , Mahadevan Rajagopalan , Yonghong Song , Vikram Rao
发明人： Partha P Tirumalai , Spiros Kalogeropulos , Mahadevan Rajagopalan , Yonghong Song , Vikram Rao
IPC分类号： G06F9/45 , G06F15/00
CPC分类号： G06F8/4442 , G06F9/3455 , G06F9/383
摘要： One embodiment of the present invention provides a system that generates code to perform anticipatory prefetching for data references. During operation, the system receives code to be executed on a computer system. Next, the system analyzes the code to identify data references to be prefetched. This analysis can involve: using a two-phase marking process in which blocks that are certain to execute are considered before other blocks; and analyzing complex array subscripts. Next, the system inserts prefetch instructions into the code in advance of the identified data references. This insertion can involve: dealing with non-constant or unknown stride values; moving prefetch instructions into preceding basic blocks; and issuing multiple prefetches for the same data reference.
摘要翻译：本发明的一个实施例提供一种生成用于对数据引用进行预期预取的代码的系统。在操作期间，系统接收要在计算机系统上执行的代码。接下来，系统分析代码以识别要预取的数据引用。该分析可以涉及：使用两相标记过程，其中确定执行的块在其他块之前被考虑; 并分析复杂的数组下标。接下来，系统在预先识别的数据引用之前将预取指令插入到代码中。该插入可以涉及：处理非常数或未知步幅值; 将预取指令移动到前面的基本块中; 并为相同的数据引用发出多个预取。

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