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31. 发明申请

US20070189097A1 Methods and arrangements for enhancing power management systems in integrated circuits 有权
标题翻译：集成电路中增强电源管理系统的方法和安排
公开(公告)号：US20070189097A1
公开(公告)日：2007-08-16
申请号：US11352699
申请日：2006-02-13
申请人： Jente Kuang , Hung Ngo
发明人： Jente Kuang , Hung Ngo
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/14
摘要： Methods and arrangements to configure power management systems for integrated circuits are provided herein. A group of IC components that are functionally distinct or have mutually exclusive and/or quasi-mutually exclusive, (ME/QME) operating patterns (i.e. alternate or partially overlapping duty cycles) can be powered with a single power cell. An integrated circuit design tool can identified components in an integrated circuit design that have the ME/QME operating patterns. These cells can be collocated in close proximity to each other and power management system components can be placed in this area such that a multiple signal processing cells can share a single power line and a single power cell. Such a configuration can greatly reduce the size of a power management system for an integrated circuit.
摘要翻译：本文提供了为集成电路配置电源管理系统的方法和布置。功能上不同或具有互斥和/或准互斥（ME / QME）操作模式（即交替或部分重叠占空比）的一组IC组件可以由单个功率单元供电。集成电路设计工具可以识别具有ME / QME操作模式的集成电路设计中的组件。这些电池可以彼此靠近并置，并且功率管理系统组件可以放置在该区域中，使得多个信号处理单元可以共享单个电源线和单个功率单元。这种配置可以大大减小用于集成电路的电力管理系统的尺寸。

32. 发明申请

US20060178037A1 Strain relief for ball grid array connectors 有权
标题翻译：球栅阵列连接器应力消除
公开(公告)号：US20060178037A1
公开(公告)日：2006-08-10
申请号：US11051361
申请日：2005-02-04
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H01R13/58
CPC分类号： H01R12/7029 , H01R12/707
摘要： Strain relief devices for electrical connectors are disclosed and include an insert for insertion into a housing. The insert may include spring beams that deflect during insertion into the strain relief housing. When the insert is fully received in the housing, a slot in the housing may be shaped such that the spring beams return to a relaxed state, locking the insert in the housing. Alternatively, an end of a strain relief insert may be inserted into the housing until beams on the strain relief insert abut shoulders in the slot in the housing. The end may protrude beyond the housing, creating a tab that may be deformed or bent to prevent the insert from moving in a direction opposite the direction of insertion.
摘要翻译：公开了用于电连接器的应变消除装置，并且包括用于插入壳体的插入件。插入件可以包括在插入应变消除壳体期间偏转的弹簧梁。当插入件完全容纳在壳体中时，壳体中的狭槽可以成形为使得弹簧梁返回到松弛状态，将插入件锁定在壳体中。或者，应变消除插入件的端部可以插入壳体中，直到应变消除插入件上的梁抵靠在壳体中的槽中。端部可以突出超过壳体，产生可能变形或弯曲的突片，以防止插入件沿与插入方向相反的方向移动。

33. 发明申请

US20060055391A1 Power-gating cell for virtual power rail control 有权
标题翻译：用于虚拟电源轨控制的电源门控单元
公开(公告)号：US20060055391A1
公开(公告)日：2006-03-16
申请号：US10926597
申请日：2004-08-26
申请人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
发明人： Jente Kuang , Jethro Law , Hung Ngo , Kevin Nowka
IPC分类号： F02P3/02
CPC分类号： H03K19/0016
摘要： Virtual power-gated cells (VPC) are configured with control circuitry for buffering control signals and a power-gated block (PGB) comprising two or more NFETs for virtual ground rail nodes and PFETs for virtual positive rail nodes. Each VPC has a control voltage input, a control voltage output, a node coupled to a power supply voltage potential, and a virtual power-gated node that is coupled and decoupled from the power supply potential in response to logic states on the control input. The control signals are buffered by non-power-gated inverters before being applied to the input of a PGB. VPCs may propagate a control signal that is in phase with or inverted from a corresponding control signal at the control input. VPCs may be cascaded to create virtual power rails in chains and power grids. The control signals are latched at the cell boundaries or latched in response to a clock signal.
摘要翻译：虚拟功率门控单元（VPC）配置有用于缓冲控制信号的控制电路和包括用于虚拟接地轨道节点的两个或更多个NFET的功率门控块（PGB），以及用于虚拟正轨节点的PFET。每个VPC具有控制电压输入，控制电压输出，耦合到电源电压电位的节点以及响应于控制输入上的逻辑状态与电源电位耦合和去耦合的虚拟电源门控节点。在施加到PGB的输入之前，控制信号由非电源门控的逆变器进行缓冲。 VPC可以传播与控制输入处的相应控制信号同相或反相的控制信号。 VPC可以级联以在链和电网中创建虚拟电源轨。控制信号在单元边界被锁存或响应于时钟信号锁存。

34. 发明申请

US20050168295A1 Interleaved VCO with body voltage frequency range control 失效
标题翻译：交错VCO与车身电压频率范围控制
公开(公告)号：US20050168295A1
公开(公告)日：2005-08-04
申请号：US10763093
申请日：2004-01-22
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03K3/03 , H03B1/00
CPC分类号： H03K3/0315
摘要： An interleaved VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. The feedforward inverting stages comprise a complementary inverter stage and a voltage controlled transfer gate. Complementary control voltages are coupled to the gates of the complementary transfer gate FET devices. Likewise, the complementary control voltages are coupled to the corresponding body of the FET devices in the transfer gate and in the inverting stage. The complementary control voltages may also be connected to the body of the complementary FET devices in the inverting stages making up the basic ring oscillator. This allows the frequency range of the VCO to be extended without having to switch the feedforward paths into an out of the circuit.
摘要翻译：使用环形振荡器配置交错VCO，该环形振荡器具有耦合在构成基本环形振荡器的反相级周围的压控前馈反相级，以使环形振荡器的频率能够被电压控制。前馈反相级包括互补反相器级和压控传输门。互补控制电压耦合到互补转移栅极FET器件的栅极。同样，互补控制电压耦合到传输门和反相级中的FET器件的相应体。互补控制电压也可以连接到构成基本环形振荡器的反相级中的互补FET器件的主体。这允许VCO的频率范围扩展，而不必将前馈路径切换到电路外。

35. 发明申请

US20050127949A1 LOW SWITCHING POWER LIMITED SWITCH DYNAMIC LOGIC 失效
标题翻译：低开关电源有限公司开关动态逻辑
公开(公告)号：US20050127949A1
公开(公告)日：2005-06-16
申请号：US10733936
申请日：2003-12-11
申请人： Hung Ngo , Jente Kuang
发明人： Hung Ngo , Jente Kuang
IPC分类号： H03K3/356 , H03K19/096
CPC分类号： H03K19/0963 , H03K3/356121
摘要： An LSDL circuit is improved by having the data input function to control the pre-charging of the dynamic node. The clock signal no longer is coupled to the P channel FET used to pre-charge the dynamic node. Additionally an N channel FET (NFET) is added in parallel with the NFET coupled to the clock for evaluating the dynamic node. This NFET assures the dynamic node does not float when the data input is a logic one and the clock is a logic zero.
摘要翻译：通过具有数据输入功能来控制动态节点的预充电来改进LSDL电路。时钟信号不再耦合到用于对动态节点预充电的P沟道FET。此外，N沟道FET（NFET）与耦合到时钟的NFET并联并用于评估动态节点。该NFET保证当数据输入为逻辑1且时钟为逻辑0时，动态节点不浮动。

36. 发明申请

US20050110578A1 Voltage controlled oscillator with selectable frequency ranges 失效
公开(公告)号：US20050110578A1
公开(公告)日：2005-05-26
申请号：US10718062
申请日：2003-11-20
申请人： Hung Ngo , Gary Carpenter
发明人： Hung Ngo , Gary Carpenter
IPC分类号： H03K3/03 , H03L7/099 , H03L7/00
CPC分类号： H03K3/0315 , H03L7/0995 , H03L7/0997 , H03L2207/06
摘要： A VCO is configured using a ring oscillator with voltage controlled feedforward inverting stages coupled around the inverting stages making up the basic ring oscillator to enable the frequency of the ring oscillator to be voltage controlled. A latch and multiplexer is used to select between two or more outputs within the ring oscillator to change the basic frequency range of the VCO glitch free. To achieve a wide range VCO, additional stages are added to the basic ring oscillator. When the number of stages is an odd number greater than seven, then the voltage controlled feedforward inverting stages feedback to the outputs of the first and second inverting stages of the ring oscillator. Two additional multiplexers are added to select which feedforward inverting stage is coupled to the first and second inverting stage. This allows a wide range interleaved VCO that switches between frequency ranges glitch free.

37. 发明申请

US20050102346A1 Computing carry-in bit to most significant bit carry save adder in current stage 失效
标题翻译：计算进位位到当前阶段的最高有效位进位保存加法器
公开(公告)号：US20050102346A1
公开(公告)日：2005-05-12
申请号：US10702992
申请日：2003-11-06
申请人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
发明人： Wendy Belluomini , Ramyanshu Datta , Jente Kuang , Chandler McDowell , Robert Montoye , Hung Ngo
IPC分类号： G06F7/50 , G06F7/60
CPC分类号： G06F7/607
摘要： A 4-to-2 carry save adder with a reduction in the delay of outputting the sum and carry bits. The 4-to-2 carry save adder may include a lower order full order coupled to a higher order full adder. The carry save adder may further include a logic unit coupled to the higher order full adder where the logic unit is configured to generate a carry bit to be inputted to the higher order full adder that normally would be generated from the carry save adder located in the previous stage. By generating this carry bit (carry-in bit) in the current stage and not in the previous stage, the delay of the carry-in bit inputted to the higher order full adder is reduced thereby reducing the delay of outputting the sum and carry bits by the higher order full adder.
摘要翻译：一个4对2进位存储加法器，减少输出和输入位的延迟。 4对2进位存储加法器可以包括耦合到较高阶全加器的较低阶满载。进位保存加法器还可以包括耦合到高阶全加器的逻辑单元，其中逻辑单元被配置为产生要输入到通常将从位于该位置的进位保存加法器产生的高阶全加器的进位位前一阶段通过在当前阶段而不是在前一阶段生成该进位位（进位位），减少输入到较高阶全加器的进位位的延迟，从而减少输出和和输出位的延迟由高阶全加器。

38. 发明申请

US20050058404A1 Guide boot for a fiber-optic cable 失效
公开(公告)号：US20050058404A1
公开(公告)日：2005-03-17
申请号：US10958847
申请日：2004-10-05
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： G02B6/38 , G02B6/36
CPC分类号： G02B6/3887
摘要： A preferred embodiment of a guide boot for a fiber-optic cable mechanically coupled to a connector comprises a mating portion having an interior surface defining a passage for receiving a portion of the connector and the fiber-optic cable, and a plurality of ribs formed on the interior surface and extending along at least a portion of a length of the mating portion. A preferred embodiment of a guide boot also comprises a body portion adjoining the mating portion and having an interior surface that defines a passage for receiving the fiber-optic cable. The interior surface of the body portion is curved so that the body portion bends the fiber-optic cable.

39. 发明申请

US20050052203A1 DUO-MODE KEEPER CIRCUIT 失效
标题翻译： DUO模式保持器电路
公开(公告)号：US20050052203A1
公开(公告)日：2005-03-10
申请号：US10655376
申请日：2003-09-04
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H03K19/096
CPC分类号： H03K19/0963
摘要： LSDL logic is provided with circuitry that has logic controls to provide two modes of operation. The half latch and the PFET that normally forms the keeper function on the dynamic node are modified. The inverter function of the series connected PFET and NFET have their corresponding positive and negative power supply terminals coupled to logic gates. In this way, the inverter may be turned ON so that the half latch functions as a keeper or it may be turned OFF to remove it from operating at all in the mode where the LSDL logic circuit needs to operate with a fast pulse clock. Likewise, the positive supply voltage may be removed while allowing the NFET device to operate to turn ON the PFET pull-up device for burn-in operation.
摘要翻译： LSDL逻辑提供有具有逻辑控制以提供两种操作模式的电路。通常在动态节点上形成保持器功能的半锁存器和PFET被修改。串联PFET和NFET的反相器功能的相应的正负电源端子耦合到逻辑门。以这种方式，逆变器可以被接通，使得半锁存器用作保持器，或者它可以被关断以使其在LSDL逻辑电路需要以快速脉冲时钟运行的模式下完全运行。同样地，可以去除正电源电压，同时允许NFET器件操作以接通PFET上拉器件以进行老化操作。

40. 发明申请

US20070202746A1 COVERS FOR ELECTRICAL CONNECTORS 有权
公开(公告)号：US20070202746A1
公开(公告)日：2007-08-30
申请号：US11348784
申请日：2006-02-07
申请人： Hung Ngo
发明人： Hung Ngo
IPC分类号： H01R13/648
CPC分类号： H01R13/506 , H01R12/724
摘要： A cover for an electrical connector includes substrate mounting beams. When a force is applied to the top, the beams transfer the force to the lead frame, pressing contacts of the connector to an electrical device such as a substrate. Flat rock application may be applied to the top of the cover to connect the connector to a substrate. The cover may aid in retaining the lead frame assemblies in the connector. A cover for an electrical connector may include a back extending from a top such that the back includes resiliency and is able to be flexed while the cover is placed on a connector and flexed to remove the cover from the connector.

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